Adv Antest Corporation

Kosuke Miyao

Don Lee

Daniel Lam

Roger Mcaleenan

Donald M Lee

Heidi Barnes

Bela Szendrenyi

Vanessa Bischler

Embodiments described herein perform incisions along the direction of the long axis of the waveguide, thereby exposing a trench structure which can be readily plated. Once divided and plated, the individual cut pieces can then be secured together to restore the original waveguide structure. In this fashion, multiple cut pieces can be secured together and used as 'building blocks' to create a modular solution which can be used to provide a number of different customizable waveguide structures. Thus, embodiments described herein can perform plating procedures in a less expensive manner while achieving the benefits of ganged waveguide structures. Moreover, embodiments described herein can offer a modular approach to ganged waveguide design thereby allowing for end-user flexibility in testing.

Plating methods for modular and/or ganged waveguides for automatic test equipment for semiconductor testing

Embodiments of the present disclosure utilize customizable waveguide fabrication technologies (e.g., 3D printer technology) and patch antenna arrays to create adaptable wave interfaces that can provide efficient signal routing for an ATE system. In this fashion, embodiments of the present disclosure allow for arbitrary waveguide routing from port to port and create high density port spacing at the PCB level and which specifically eliminates the large flange required of prior art waveguides. Furthermore, embodiments include the ability to integrate different waveguide components, including power splitters, couplers, terminations, etc., into a single structure. Thus, embodiments of the present disclosure can reduce signal path losses and simplify the mechanical construction of ATE systems while eliminating the need for coax cables and minimizing the length of PCB microstrips.

Wave interface assembly for automatic test equipment for semiconductor testing

Embodiments of the present disclosure use customizable waveguides that can be positioned next to each other in a structure that contains one single flange to provide a physical connection for the waveguides. In this fashion, many waveguides can be positioned within a small area to accommodate a tightly packed patch antenna array so that the waveguides can be positioned very close to the socket. As such, embodiments of the present disclosure allow more waveguides to be packed into a small area by providing a single structure that houses many waveguides and share only a single flange connection element that can be sized appropriately.

Multiple waveguide structure with single flange for automatic test equipment for semiconductor testing

A structure for signal transmission is disclosed. The structure comprises a first plurality of waveguides tightly disposed together and disposed substantially in parallel with each other, each of said waveguides having a first opening and a second opening, wherein each first opening is operable to align with a patch antenna, and wherein the first plurality of waveguides is disposed adjacent to a socket. The integrated structure further comprises the socket which comprises an opening operable to support an insertion of a device under test (DUT), wherein the DUT is communicatively coupled to a plurality of microstrip transmission lines on a printed circuit board (PCB) underlying the socket for transmitting test signals from the DUT, wherein each of the microstrip transmission lines is electrically coupled to a respective patch antenna. Further, the first plurality of waveguides and the socket are integrated into a single plastic or metal structure.

Integrated waveguide structure and socket structure for millimeter waveband testing

A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port.

Growing community of inventors

San Jose, CA, United States of America

Kosuke Miyao