Intel Corporation

Kosta Luria

Michael Zelikson

Efraim Rotem

Doron Rajwan

Alon Naveh

Alexander Gendler

Joseph Shor

Jorge Pedro Rodriguez

Joseph T Dibene, Ii

Edward R Stanford

Hung-Piao Ma

Annabelle Pratt

Arye Albahari

Gil Schwarzband

Sean M Welch

Lior Gil

Ohad Nachshon

Dan Baum

Alexander Lyakhov

Ronny Korner

Avinash N Ananthakrishnan

Nadav Shulman

Dorit Shapira

Omer Vikinski

Dadashev Oleg

Vadim Goldenberg

Dorit Shpira

A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

DLVR-supplied logic domain operational voltage optimization

Some embodiments include an apparatus including a first node in a voltage regulator, a second node in the voltage regulator, and a power stage to receive a first voltage from the first node and provide a second voltage at the second node. The power stage includes a first circuit path and a second circuit path coupled in parallel with each other between the first and second nodes. The first circuit path includes a first number of at least one transistor coupled between the first and second nodes. The second circuit path includes a second number of at least one transistor between the first and second nodes. Wherein the first number is unequal to the second number.

Digital voltage regulator including mixed-stack power stage

The circuits and methods described herein provide technical solutions for technical problems facing power driver circuits. To reduce or eliminate effects associated with a gate capacitance discharge current and inconsistent effective V, the discharge process may be split into two phases. During a first phase, the transistor gate charge is drained into ground through a large path gate. The ground (GND) features a very low impedance, hence the resulting δV(t)|is negligible even for high discharge currents. The transistor gate node voltage (V) is constantly monitored, and the discharge process switches from the first phase to the second phase when Vtransgresses a bias voltage threshold based on the target value of V. To switch from the first phase to the second phase, the current path into GND is cut by switching its path gate to an OFF state, and an alternative path is enabled between transistor gate charge and V.

Efficient switching of output stage power driver

Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Low dropout voltage regulator integrated with digital power gate driver

A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.

Current sensor based closed loop control apparatus

In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

Apparatus and method to track device usage

An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.

Apparatus and method for high current protection

Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.

Simultaneous multi-voltage rail voltage regulation messages

Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

Power management for processing unit

In some embodiments, a new DTS implementation, which employs the conventional Vbe/&#x394;Vbe temperature dependent principles but substitutes a voltage-to-frequency (V/F) based ratio meter for the DAC based approach. This new approach can result in a more simplified circuit that may be more variation tolerant and can require less power and area.

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Pardesiya, Israel

Kosta Luria