Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kosei Okamoto

Akihisa Fujimoto

Hiroyuki Sakamoto

Masao Suga

Hideyuki Toma

Mitsuaki Moritani

Shinji Yamadaji

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Electronic device with card interface

In one embodiment, a system having a non-volatile programmable memory and a controller is provided. The system has data pins that are configured to be accessed in one of a first mode and a second mode such that, in the first mode, the system receives information using one of the data pins and, in the second mode, the system receives information using four of the data pins. The system also has a command pin that is configured to receive a first command, a second command, and a third command, the first command requesting a current operation mode of the data pins, the second command requesting operation voltage information of the system, and the third command setting the system into one of the first and second modes. Additionally, the system has a power signal pin configured to receive power for the system.

Programmable memory system

When initializing a device, an operation mode of the device is acquired and stored by a predetermined procedure using a predetermined pin. In response to a command, the device executes a signal assignment on a plurality of data pins peculiar to an operation mode indicated by the received command, thereby switching a data transfer width, and allowing the device to operate in the operation mode designated by the received command.

This invention provides an on-vehicle electronic apparatus, which has a wireless communication unit which makes a wireless communication via a wireless LAN, means for acquiring position information and velocity information of vehicles before and after the self vehicle using the wireless communication unit, means for calculating the inter-vehicle distances between the self vehicle, and the vehicles before and after the self vehicle with reference to map information on the basis of the acquired position information and velocity information, and means for, when the calculated inter-vehicle distances are equal to or smaller than a predetermined distance and the velocities of the self vehicle and the vehicles before and after the self vehicle are equal to or higher than a predetermined velocity, taking a collision avoidance measure.

On-vehicle electronic apparatus

An instruction pipeline type microprocessor comprises an operation execution section consisting of a first operation execution section for executing instructions having no memory operand, a second operation execution section for executing instructions having a memory operand, and a third operation execution section for executing floating point instructions. A general purpose register is provided consisting of a second register group for storing data processed as a result of execution by the operation execution section in the form of a flow of programs and a first register group for storing processed data as the result of a look-forward execution of instructions which can be processed by the operation execution section. Compare logic determines whether or not succeeding instructions have been executed. The processed data held in the first register group is provided to the second register group so as to facilitate execution in the predetermined program order.

Instruction pipeline microprocessor

An interrupt control apparatus of a microprocessor comprises a controller for selecting an interrupt requirement having a highest priority from a plurality of interrupt requirements and outputting the signals indicative of this highest priority; a comparator for comparing the priority of the interrupt requirement selected by the interrupt controller with mask information indicating a priority as to whether the interrupt requirement is executed or not; a detector for detecting whether the priority of the interrupt requirement is outputted from the controller or not; and a judging device for stopping an output of the controller when the priority of the selected interrupt requirement is lower than the priority of the mask information. The judging device makes the controller further select an interrupt requirement having a highest priority from the plurality of interrupt requirements by the controller and output a signal indicative of this priority when the detector detects the stoppage of the output of the controller. The judging device instructs the execution of the selected interrupt requirement when the priority of the selected interrupt requirement is higher than or equal to the priority of the mask information.

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Kunitachi, Japan

Kosei Okamoto