Hitachi, Ltd.

Kosei Nomiya

Hiroto Kawagoe

Takao Tsuiki

Shinkichi Hotta

Toshihiko Kohisa

Isao Matsumura

Yoshikazu Hatsukano

Tadao Kikuchi

Takeshi Kobayashi

An input circuit has at least an enhancement type first MISFET incorporated between an input terminal and a power supply terminal for the input circuit. A gate electrode of the first MISFET is connected to the power supply terminal, and at least a second MISFET is incorporated between the input terminal and a gate electrode of a third MISFET constituting the input circuit. A gate electrode of the second MISFET is connected to the power supply terminal, whereby the dielectric breakdown of the gate of the third MISFET is prevented.

Input circuit

A key input circuit includes a binary-coded N-ary counter consisting of a plurality of binary counters, a decoder decoding coded pulse outputs of the counter for converting the counter outputs into a plurality of timing pulse signals, which are applied respectively to a plurality of keys. These timing pulse signals form a key information input by manipulation of the corresponding key, and a plurality of gates are provided for coding the key information by gating the input provided by the specific coded pulse output of the counter in response to receipt of the control input provided by the specific key signal applied through the manipulated key.

Key input circuit

A constant current driving circuit for driving light emitting diodes, wherein a variation detecting circuit comprising a resistor and a field effect transistor is provided and the output voltage of the detecting circuit is effectively used to control the variation of electric current which flows through the driving transistor.

Constant current driving circuit

Described are insulated gate-type field effect transistors used in capacitive memory circuits and having protective diodes for protecting the insulating films below the gate electrodes from electrical breakdown, in which parasitic transistor action which might be caused by minority carriers injected into semiconductor substrates by noise signals applied to the protective diodes are eliminated by means for suppressing injection of minority carriers or by means for preventing injected minority carriers from reaching the drain regions of the field effect transistors.

IGFET with gate protection diode and antiparasitic isolation means

In an information processing system controlled systematically by a programable logic array, the initialization of the contents of a predetermined memory circuit after switching-on the power is effected by setting the contents of the memory circuit to an initial value by means of a signal generated automatically or manually.

Information processing system

An input gate circuit of a semiconductor integrated circuit composed of insulated gate field-effect transistors, comprises a driving transistor and a load transistor which form an inverter, a transistor which prevents the input of the integrated circuit from being opened, and resistance means to protect the transistors. A first resistance is connected in series between an input terminal and the gate of the driving transistor, while another resistance is connected between the input terminal and one end of the input opening preventing transistor whose other end is connected to a power supply terminal.

Gate circuit

In order to provide compensation for changes in the ambient temperature and supply voltage for an electronic circuit, such as a pulse generator circuit made up of MOSIC structure, a field effect transistor circuit includes a high value resistor and an enhancement and depletion type MOSFET, connected in parallel. The drain electrodes of the MOSFETs are connected to the power supply through the resistor and are also connected to the gate electrode of a depletion type load MOSFET which is the load transistor for an enhancement type MOSFET. When the compensating circuit is provided in a pulse generator circuit, instability in the oscillating frequency of the pulse generator due to changes in ambient temperature and supply voltage is overcome and the difference in the oscillating periods for the various MOSICs are decreased.

Electronic circuit using field effect transistor with compensation means

A digital display system of the dynamic pulse-lighting type for electronic desk-top calculators and the like, characterized in that a blanking signal having a pulse width large enough to cover each border time between adjacent display timing signals is used to shut off the power supply to the display devices for each pulse duration to suppress any flicker of the display unit which might otherwise result from non-synchronism or overlapping of the display signals.

Arrangement for a dynamic display system

A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a delay by the second delay circuit, whereby the output signal is made apparently free from the delays due to the preceding stage or stages and to the memory and logical circuits.

Digital circuit to eliminate display flicker

Insulated gate-type field effect transistors used in capacitive memory circuits and having protective diodes for protecting the insulating films below the gate electrodes from electrical breakdown, in which parasitic transistor action which might be caused by minority carriers injected into semiconductor substrates by noise signals applied to the protective diodes are eliminated by means for suppressing the injection of minority carriers or by means for preventing injected minority carriers from reaching the drain regions of the field effect transistors.

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Tokyo, Japan

Kosei Nomiya