Broadcom Corporation

Koray Oner

Laurent Rene Moll

Manu Gulati

Joseph Byron Rowlands

Barton Sano

James B Keller

James D Kelly

Jeremy Dion

The present application discloses a memory controller for accessing an external memory device. The memory controller comprises a bus interface and an internal memory buffer capable of accessing the bus interface. The internal memory buffer operates as an on-chip storage. In various embodiments of the disclosure, the internal memory buffer operates during a testing of a chip containing the memory controller. For example, the internal memory buffer may emulate the external memory device in response to an input signal. Moreover, in various embodiments of the disclosure, the external memory device may be a dynamic random access memory (DRAM), while the internal memory buffer may be a static random access memory (SRAM). The memory controller may be adapted to automated test equipment (ATE). Moreover, the memory controller may be incorporated onto a system-on-a-chip (SOC) along with one or more agents.

Memory controller with emulative internal memory buffer

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.

Packet manager interrupt mapper

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a channelized timer for use in controlling the issuance of signals to the processor(s) or control logic (such as interrupts, descriptors, etc.) that that identify system-related functions for a plurality of channels. Using control registers to select an individual bit of a multi-bit counter, a timing interval pulse is provided for prompting signal generation that is otherwise subject to a minimum count requirement.

Exponential channelized timer

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor write back timer mechanism for use in efficiently writing descriptors back to memory after transmitting data under control of the descriptors to inform the processor(s) about system-related functions for a plurality of channels. A timing interval pulse is provided for prompting descriptor write back operations that are otherwise subject to a minimum descriptor count requirement.

Descriptor write back delay mechanism to improve performance

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

Fragment storage for data alignment and merger

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Descriptor-based load balancing

A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.

Data pend mechanism

A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

Addressing scheme supporting variable local addressing and variable global addressing

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

System having interfaces and switch that separates coherent and packet traffic

An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

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Sunnyvale, CA, United States of America

Koray Oner