Qimonda North America Corporation

Qimonda Ag

KoonHee Lee

Klaus Nierle

Hoon Ryu

Ryan Patterson

A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Apparatus and method for manufacturing a multiple-chip memory device with multi-stage testing

A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

System and method for addressing errors in a multiple-chip memory device

An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal.

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South Burlington, VT, United States of America

KoonHee Lee