Mitsubishi Electric Research Laboratories, Inc.

Other

Mitsubishi Electric Corporation

Murata Manufacturing Co., Ltd.

Koon Hoo Teo

Jinyun Zhang

Rui Ma

Bingnan Wang

Neelesh B Mehta

Chungwei Lin

Nadim Chowdhury

Chunjie Duan

Qiuyao Zhu

William Yerazunis

Zhifeng Tao

SungWon Chung

Da Huang

Philip Orlik

Zafer Sahinoglu

Yuhao Zhang

Yi Deng

Nadim Chowdhurry

Toshiaki Koike-Akino

Dehong Liu

Zhengyu Peng

Toshiyuki Kuze

Amine Maaref

Peijie Feng

Hongyuan Zhang

Andreas F Molisch

Jianlin Guo

Ming Sun

Yebin Wang

Pu Wang

Kyeong Jin Kim

Toshiyuki Oishi

Ghulam Bhatti

Andrei Kniazev

Man-On Pun

Lei Zhou

Yves-Paul Nakache

Makoto Kanemaru

Shigeru Uchida

Daniel Antonio Da Costa Dinis

Chenjie Tang

Vishwanath Iyer

Jia Tang

Kyeongjin Kim

Sushmit Goswami

Ehsan Azarnasab

Jianjian Wang

Kentarou Sawa

Yingda Chen

Qun Gao

Jin Shao

Shen Zhang

Toshiaki Akino

Jiang Long

Pin Chun Shen

Pin-Chun Shen

Xusheng Sun

Gennadiy V Vinokur

Ronghui Peng

David Ellstein

Nakayama Masatoshi

Rong-Rong Chen

Behrouz Fahang

Sheikh Nijam Ali

Xuehong Mao

Chun Kin Au Yeung

Philip V Orlik

Pinchun Shen

Yves-Paul N Nakache

Devices and methods of a transistor device including a source and a drain, the source and drain are at a horizontal plane at a location along a vertical direction. A gate, that is at a higher horizontal plane along the vertical direction then the source and drain horizontal plane. A first region under the source and drain horizontal plane, includes a first three Nitride (III-N) layer, a second III-N layer over the first III-N layer. A second region under the gate, includes a first III-N layer, a second III-N layer over the first III-N layer, and a third III-N layer over the second III-N layer. The third III-N layer at selective locations extends through the second III-N layer and into a portion of the first III-N layer along a width of the transistor. The third III-N layer is doped P-type, and the first and second III-N layers are unintentionally doped.

Super junction gated AlGaN GaN HEMT

Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

Inverter based on electron interference

A motor comprising a shaft, an array of stator assemblies rigidly attached to the shaft, each stator assembly includes a stator yoke having a toroid shape fixed around the shaft and having a number of slots at radial and axis directional faces with windings within the slots of the stator yoke, and a rotor assembly rotatively attached to the shaft to enclose the array of stator assemblies, the rotor assembly has a rotor drum with sections, each section embraces one stator assembly, each section has two axial-flux permanent magnet arrays attached on axial-directional inner surfaces of the section and has one radial-flux permanent magnet array attached on a radial-directional inner surface of the section furthest from the shaft, wherein the axial-flux and the radial-flux permanent magnet arrays with the number of pole pairs equals the number of the stator slots plus or minus the number of stator winding pole pair.

Multi-layer axial and radial flux vernier permanent magnet motor

An AND-gate device having a structure arms, a channel from a first arm and a second arm extends to a channel of a third arm. When a current from a first voltage flowing from a first electrode of the first arm to a second electrode of the second arm, a flow of electrons is generated that flows through the third arm channel from the channel of the first and second arms to the third arm channel. At least two input structures are positioned in series in the third arm. Each input structure includes a fin structure having a gate controlled by an individual voltage applied to an electrode which induces an electric-field structure that shifts by an amount of the voltage. The controllable gate opening changes a depletion width, causing an amount of flow of ballistic electrons to pass through the channel. A sensor detects the ballistic electrons.

AND gate based on ballistic electrons

Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.

2-dimensional electron gas and 2-dimensional hole gas junction based semiconductor device

A system for estimating a severity of a bearing fault in an induction motor, uses a set of filters and a set of quantitative models designed for a set of fault frequencies. The system, upon receiving the measurements of the stator current, extracts the first fault current from the stator current using the first filter, determine the first mutual inductance variation from the first fault current using the first quantitative model, and classify the first mutual inductance variation with the fault severity classifier to determine the severity of a first type of fault in the induction motor. Similarly, the system classifies a second type of fault using the second filter and the second quantitative model. The system outputs one or combination of the severity of the first type of fault in the induction motor and the severity of the second type of fault in the induction motor.

Method for estimating bearing fault severity for induction motors

An OR-gate device includes two cross shaped structures, each cross shaped structure includes a channel. Where at an end of each channel is an ohmic contact connecting the two cross shaped structures. Each cross shaped structure includes an epitaxial layer including a III-N heterostructure such as InAlN/GaN. Wherein an amount of an In concentration of the InAlN/GaN is tuned to lattice match with GaN, resulting in electron mobility to generate ballistic electrons. A fin structure located in the channel includes a gate formed transversely to a longitudinal axis of the channel. The gate is controlled using a voltage over the fin structure. Wherein the fin structure is formed to induce an energy-field structure that shifts by an amount of the voltage to control an opening of the gate that the flow of ballistic electrons is passing through, which in turn changes a depletion width, subjecting the ballistic electrons to interference.

OR gate based on electron interference

A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Transistor with multi-metal gate

Devices, system and methods a circuit, including a resistor, a normal capacitor and a ferroelectric capacitor connected in series. An input terminal to provide an input voltage across the circuit. An output terminal to deliver an output voltage taken across the normal capacitor. The circuit comprises a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer. The first buffer layer contacts a portion of a first metal layer and first metal layer extends beyond the first buffer layer. A dielectric layer sandwiched between a second metal layer and a third metal layer. Such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer. Wherein the ferroelectric capacitor is formed by the first metal layer. The ferroelectric layer sandwiched between the first buffer layer and the second buffer layer, and the second metal layer.

Virtual inductors using ferroelectric capacitance and the fabrication method thereof

A high electron mobility transistor includes a set of electrodes, such as a source, a drain, a top gate, and a side gate, and includes a semiconductor structure having a fin extending between the source and the drain. The top gate is arranged on top of the fin, and the side gate is arranged on a sidewall of the fin at a distance from the top gate. The semiconductor structure includes a cap layer positioned beneath the top gate and a channel layer arranged beneath the cap layer for providing electrical conduction. The cap layer includes nitride-based semiconductor material to enable a heterojunction forming a carrier channel between the source and the drain.

High electron mobility transistor with tunable threshold voltage

A negative electroluminescent cooling device including a first layer of material; a second layer of material arranged at a non-zero distance from the first layer of material with help of a set of supporters, and an energy source to apply a reverse bias voltage to the first layer of material to cool the second layer of material. The material of the first layer is a semiconductor with a bandgap less or equal to a surface resonant energy of the second layer of material.

Negative electroluminescent cooling device

Devices and methods of a transistor device that include a flexible memory cell. The flexible memory cell having a gate stack with sidewalls provided over a substrate. The gate stack including a metal gate layer provided over the substrate. A buffer layer provided over the metal gate layer. A ferroelectric layer provided over the buffer layer. A dielectric layer provided over the ferroelectric layer. Further, a two-dimensional (2D) material layer provided over a portion of a top surface of the dielectric layer. Source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity that the 2D material layer are located.

Low power 2D memory transistor for flexible electronics and the fabrication methods thereof

A thermal emitter including a substrate and a grating arranged atop the substrate, the grating includes a plurality of equidistant structures having a cross-section with a trapezoid shape. Material of the substrate and the grating converts incoming heat into radiation.

Thermal emitter for energy conversion technical field

A thermoradiative device for generating power includes a thermoradiative element having a top surface and a bottom surface, wherein the thermoradiative element is a semiconductor material having a bandgap energy E. The device includes a thermal conductive element having a first surface and a second surface, wherein the first surface is arranged to face the bottom surface of the thermoradiative element, and the first surface is a structured surface having a periodic structure, wherein the structured surface is separated from the bottom surface with a distance d to establish near-field resonance between the bottom surface and the structured surface. The device further includes supporters configured to bond the thermoradiative element and the thermal conductive element.

Near-field based thermoradiative device

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Lexington, MA, United States of America

Koon Hoo Teo