Hynix Semiconductor Inc.

Kook Whee Kwak

Nak Heon Choi

Jung Eon Moon

Si Woo Lee

Hee Jeong Son

Joon Won Lee

Dae Gwan Kang

Seong Hoon Jeong

Suk Yun

Yoon Sung Lee

Yun Suk

The present invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit of the present invention includes a transfer unit that transfers electrostaticity from at least one of a plurality of input/output pads to a boost bus line, a trigger unit that responds to the electrostaticity transferred via the boost bus line to detect a trigger voltage and apply it to a trigger bus line, and a plurality of clamp units that are connected between the input/output pads and an internal circuit. The clamp units are triggered by the trigger voltage of the trigger unit to discharge electrostaticity of the input/output pads to a first or second power supply voltage line, thereby safely protecting the internal circuit from electrostatic damage and lowering the operating voltage of the clamp unit with minimum costs without increasing an area of the electrostatic discharge protective circuit within a semiconductor integrated circuit.

Electrostatic discharge protection circuit having a reduced size and lower operating voltage

An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

Electrostatic discharge protection circuit and electrostatic discharge protection method of a semiconductor memory device

An electrostatic discharge protection circuit protects the internal circuits of a semiconductor. The electrostatic discharge protection circuit includes a first electrostatic protection unit connected to a power source supply pad. The first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit. A driver driven by the first driving voltage generates a second driving voltage by an ESD current. A second electrostatic protection unit discharges the introduced ESD current into the power source supply pad by the second driving voltage such that a voltage applied to a gate of the first NMOS transistor is reduced.

Electrostatic discharge protection circuit protecting thin gate insulation layers in a semiconductor device

Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.

Electrostatic discharge protection device having a dual triggered transistor

The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and sources and drains alternately arranged at both sides of the gates in the semiconductor substrate. A well pickup surrounding every set of the transistor fingers and extending between any two set of the fingers is formed. Metal wires are connected to at least two portions of each of the drains and are also connected to an input/output pad to which Electrostatic Discharge (ESD) excessive current is introduced.

Growing community of inventors

Kyoungki-do, South Korea

Kook Whee Kwak