Samsung Electronics Co., Ltd.

Kook-hwan Kwon

Hee-Choul Park

Disclosed is a high speed semiconductor memory device, which includes a memory cell to which a pair of bit lines are coupled and a discharge circuit for sufficiently discharging one of the bit lines which is being pulled down to a low voltage level in a write operation. Thus, in spite of a short write cycle time, the write operation speed of the memory can be improved without the imperfection in writing a data into the memory cell.

High speed semiconductor memory device

A method for precharging a bit line pair or data line pair in a semiconductor memory device includes generating a precharge pulse signal when a write enable line is deactivated at the beginning of a read cycle. The line pair is rapidly precharged by a pair of large transistors which turn on in response to the pulse signal. The pulse signal ends and turns of the transistors before a word line is enabled during the read cycle to prevent the large transistors from interfering with the bit sensing operation. A precharge circuit for precharging a bit line pair or data line pair in a semiconductor memory device includes a pulse generator having a delay circuit that determines the pulse width of a precharge pulse which is generated when a write enable line is deactivated. A write and precharge circuit includes two large transistors connected between a line pair and a power source that turn on and rapidly precharge the line pair during the precharge pulse. A third large transistor is connected between the lines of the line pair to equalize the voltages of the lines when the precharge pulse is generated.

Precharge system for a semiconductor memory device

A high-speed data output related circuit for a memory device reduces the operational cycle time by self-latching data in a data output buffer and self-resetting a main sense amplifier and level shifter, thereby the need for external control signals. A data output related circuit in accordance with the present invention includes: a sense amplifier for generating sensed data; a level shifter for converting the level of the sensed data, thereby generating level shifted data; a data output buffer for self-latching the level shifted data in first latch nodes in response to the level shifted data, for latching the level shifted data latched in the first latch nodes in second latch nodes when a data passing clock is received, and for transmitting data latched in the second latch nodes through output terminals in response to an output enable signal; and a controller for sequentially activating, before the level shifted data arc generated, the operations of the sense amplifier and the level shifter by generating a main sensing enable signal and a shifting enable signal as first and second logic levels in response to a sensing enable signal supplied from the device, and for sequentially disabling, immediately after the level shifted data are self-latched, the operations of the sense amplifier and the level shifter by generating the main sensing enable signal and the shifting enable signal as second and first logic levels, thereby causing the data output buffer to be self-reset when the level shifted data are latched in the first latch nodes.

Growing community of inventors

Suwon, South Korea

Kook-hwan Kwon