Samsung Electronics Co., Ltd.

Kook-Hwan Kwon

Hee-Choul Park

Hyang-Ja Yang

Young-Ho Suh

Yong-Hwan Noh

Eun-Cheol Kim

In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

High-speed synchronous semiconductor memory having multi-stage pipeline structure and operating method

An electrostatic discharge (ESD) protection transistor for discharging current from an ESD event present on an input/output pad. The ESD protection transistor is capable of improved discharging of excessive current without damage to the semiconductor device and to the ESD protection transistor itself. The ESD protection transistor includes a first conductive line connecting an input/output pad to the source and drain of the transistor at multiple points preventing the convergence of an excessive current at a certain point and ESD damage to the transistor. The transistor also includes a second conductive line formed on an insulating layer such that it does not overlap with the first conductive line.

Electrostatic discharge protection transistor for a semiconductor chip

A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit

An internal clock generating circuit of a synchronous type semiconductor memory device includes a transmission part for transmitting a first clock enable signal in response to applying a first level of a first clock signal. It also includes a latch part for latching the first clock enable signal transmitted from the transmission part. A gating part gates the latched first clock enable signal with the first clock signal to generate a second clock signal as an internal clock signal for the memory device. This reduces a time lag by which the speed of the internal clock is synchronized with the external clock signal.

Internal clock generating circuit of synchronous type semiconductor memory device and method thereof

Methods and apparatus are disclosed for receiving and decoding address information applied to a synchronous semiconductor memory device. Separate read address and write address decoders and latches are provided for decoding the address without waiting for a determination as to whether a read cycle or a write cycle is undertaken, thereby reducing the decoding delay and thereby increasing the speed of such a device in operation.

Address decoding . . . semiconductor memory

A data output buffer circuit for a semiconductor memory device operates with two separate power supplies and prevents malfunctions caused by the sequence in which the power supplies are energized. At lease one discharge transistor is used to remove charge from the gate of one or more NMOS push-pull transistors in an output buffer which can be floating in a charged state if one of the power supplies is energized before the other. In one embodiment, the gates of two discharge transistors are cross-coupled to the gates of the push-pull transistors to assure that at least one of the push-pull transistors are turned off. In an alternative embodiment, one or more discharge transistors are connected to the gates of at least one push-pull transistor and are controlled by a pulse generator that generates a pulse signal in response to variations in the voltage of the power supply for the push-pull transistors. In another alternative embodiment, the push-pull buffer includes a PMOS push transistor and an NMOS pull transistor. An inverter, which is powered by the same power supply as the push-pull buffer, drives the gate of the PMOS transistor. Two discharge transistors are connected to the gates of the push-pull transistors, and the gates of the two discharge transistors are cross-coupled to the gate of the NMOS pull transistor and the input of the inverter to assure that at least one of the push-pull transistors are turned off.

Data output buffer for multiple power supplies

A burn-in test circuit for a semiconductor memory device tests for defective memory cells. The test circuit applies a test signal that turns 'off' transistors in a precharge circuit and applies a select signal to memory cells at predetermined intervals. The select signal and test signal are delayed for different time intervals depending on whether the memory device is transitioning from a normal operating mode to a test mode or from the test mode to the normal operating mode. The selective delay prevents overcurrent conditions from occurring during the mode transitions.

Semiconductor memory device having a burn-in control circuit and burn-in

Integrated circuit chips with fuse-based mode selection capability include a first signal generator for storing a first logic state when the fuse is blown, in response to an externally generated input signal, and for generating a first option changing signal based on the stored first logic state. To reduce the susceptibility to noise and inadvertent designation signals, a second signal generator for storing a second logic state when the fuse is blown is also provided and that fuse is blown in response another externally generated input signal. However, rather than blowing the fuses of the first option changing signal generator and the second option changing signal generator by applying external input signals simultaneously, the fuses are blown sequentially by connecting the second option changing signal generator in series with the first option changing signal generator so that the second option changing signal cannot be generated unless the first option changing signal generator has already been generated. To further lessen the likelihood of inadvertently blowing a fuse, thereby causing a reduction in yield of an integrated circuit semiconductor device, the first option changing signal generator is also connected in series with a dummy option changing signal generator. This dummy option changing signal generator is used to prevent the inadvertent generation of the first logic state caused by a blown fuse in the first option changing signal generator. The first and second option changing signals are then provided to a functional circuit to designate an active mode.

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Kyonggi-do, South Korea

Kook-Hwan Kwon