Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Konrad Wagensohner

Markus Georg Rommel

Michael Uwe Schlenker

Marco Corsi

Donald Charles Abbott

Taylor R Efland

Erich Bayer

Louis N Hutter

Chi-Cheong Shen

John P Erdeljac

Charles E Williams

Quang X Mai

Walter Bucksch

Rebecca Grancaric

Markus Matzberger

Ross Eliot Teggatz

Joseph A Devore

Stefan Herzer

Gerhard Thiele

Milton Lee Buschbom

Josy Bernard

Hongcheng Xu

Annabelle Arnold

Michael Schlenker

Anton Winkler

A circuit may include a current generator coupled to a first voltage source. The current generator may be configured to generate a first current, and mirror the first current into a second current and a third current. The circuit may include a proportional to absolute temperature ('PTAT') voltage generator coupled to the current generator and a second voltage source. The PTAT voltage generator may be configured to receive the second current from the current generator, and generate a third voltage based on the second current. The circuit may include a complementary to absolute temperature (“CTAT”) voltage generator coupled to the current generator and to the PTAT voltage generator. The CTAT voltage generator may be configured to receive the first current and the third current from the current generator, and generate a reference voltage based on the first current, the second current, and the third voltage.

Reference voltage generation within a temperature range

Described embodiments include a circuit with a first amplifier having first and second amplifier inputs and a first amplifier output. The first amplifier input is coupled to a reference voltage terminal. The second amplifier input is coupled to a voltage feedback terminal. A second amplifier has third and fourth amplifier inputs and second and third amplifier outputs. The third amplifier input is coupled to the first amplifier output. A first switch has first and second switch terminals. The second switch terminal is coupled to the fourth amplifier input. A third amplifier has fifth and sixth amplifier inputs and a fourth amplifier output. The fifth amplifier input is coupled to the second amplifier output. The sixth amplifier input is coupled to the third amplifier output. A second switch has a third switch terminal coupled to the fourth amplifier output, and a fourth switch terminal coupled to the first amplifier output.

Skip clamp circuit for DC-DC power converters

Apparatus and systems and articles of manufacture are disclosed to provide adaptive leakage compensation for powertrains. An example apparatus comprising a first current path including a first transistor and a second transistor; a second current path including a third transistor and a fourth transistor; and a current mirror including a fifth transistor and a sixth transistor, wherein a first ratio exists between the first transistor and the third transistor, a second ratio exists between the second transistor and the fourth transistor, and a third ratio exists between the fifth transistor and the sixth transistor, the third ratio greater than or equal to the second ratio, the second ratio greater than or equal to the first ratio.

System and apparatus to provide current compensation

An integrated circuit comprising: a source comprising an output port; a set of serially-connected resistors electrically coupled to the output port of the source; a comparator comprising a first input port, a second input port, and an output port; a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; a current source comprising an output port electrically coupled to the second input port of the comparator; and a pin electrically coupled to the output port of the current source.

Integrated circuits with a set of serially-connected resistors

A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source.

Low power switching DC-DC converter and method of the same

A DC-DC converter has high-side power and low-side power transistors connected in series between supply terminals, an inductor connected between the power transistors and an output terminal. A comparator compares the output voltage with a reference voltage. A detector detects when inductor current approaches zero. A timer is configured to determine a minimum ON time of the high-side power transistor optimized for a particular value inductor. A current detector detects current flow in the back-gate diode of the low-side power transistor. timer is configured to determine an overriding ON time in response to the back-gate current detector. Logic provides control signals to gate power transistors in response to the comparator and the longer one of the minimum ON time and the overriding ON time. The minimum ON time for the high-side power transistor is adjusted in response to the actual inductance of the inductor.

DC-DC converter with automatic inductor detection for efficiency optimization

A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to the pin to a sequence of logic low and logic high values. The decoder comprises an up/down counter with a count input connected to a clock source, an edge detection circuit detecting rising and falling edges of the input signal. The edge detection circuit is connected to the up/down counter to start up counting from a reset value upon detection of an edge in a first direction and to start down counting from a current count upon detection of an edge in a second direction. The decoder further comprises a bit value deciding circuit that delivers a first logic value when the count of the up/down counter is above the reset value on detection of an edge in the second direction and delivers a second logic value when the count of the up/down counter is at or below the reset value on detection of an edge in the second direction.

Serial interface circuit for a single logic input pin of an electronic system

An integrated circuit device ( ) with a bonding surface ( ) directly over its active circuitry, and a method of making such integrated circuits (FIGS. A- E). To make the bonding surface ( ), a wafer ( ) is provided with vias ( ) to its metallization layer ( ) and then coated with a seed metal layer ( ). A plating pattern ( ) is formed on the wafer ( ), exposing portions of the seed metal layer ( ) and blocking the rest of the seed metal layer ( ). These exposed portions are plated with successive metal layers ( ), thereby forming a bonding surface ( ) having a number of layered stacks ( ) that fill the vias ( ). The plating pattern and the nonplated portions of the seed metal layer ( ) are then removed.

Integrated circuit with bonding layer over active circuitry

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

A circuit arrangement 10 for driving an MOS field-effect transistor QO allocated to the supply circuit KO of an electrical load R.sub.L contains a charging circuit K1 and a discharging circuit K2, which can be alternatively connected to the MOS field-effect transistor QO. A sensing circuit K3 supplies the measuring signal S.sub.M typical of gate-source voltage U.sub.GS of the MOS field-effect transistor QO, via which the internal resistance of the charging or discharging circuit K1, K2 and/or a current I.sub.a impressed upon these circuits K1, K2, in the sense of a positive feedback, is controlled, in such a way that the resulting time constant, according to which the input capacitance of the MOS field-effect, transistor QO is charged or discharged, becomes smaller during the transition of the MOS field-effect transistor QO from the off state to the conductive state and larger during the transition from the conductive to the off-state.

Circuit arrangement for driving an MOS field-effect transistor allocated

An integrated power device comprises a power transistor (26) and a plurality of sense transistors (38), (40), (42), (44), and (46). Sense transistors (38), (40), (42), and (44) are constructed around the periphery of the active area occupied by power transistor (26). Sense transistor (46) is located within the interior of the active area occupied by power transistor (26) and contact is made to the necessary source region (64) of transistor (46) using a second level of metal interconnect to form a source contact (74).

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Mauern, Germany

Konrad Wagensohner