Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.v.

Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Ag

Globalfoundries Dresden Module One Limited Liability Company & Co. Kg.

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Qimonda Flash Gmbh & Co. Kg

Konrad Seidel

Patrick Polakowski

Detlev Richter

Uwe Augustin

Thomas Kaempfe

Tarek Ali

Andreas Kux

Luca De Ambroggi

Dina Triyoso

Johannes Mueller

Andreas Taeuber

Robert Petter

Gert Koebernick

Volker Zipprich-Rasch

Reinhard Ronneberger

Mirko Reissmann

Gert Köbernik

Hans Heitzer

Daniel-André Löhr

Sören Irmer

Mario Wallisch

Franz Müller

Maximilian W Lederer

Mark Gerard Nolan

Konstantin H J Mertens

David J Lehninger

Wenke Weinreich

Marco Ziegelmayer

Memory cells include various versions of a capacitor structure including a polarization retention member. Each polarization retention member includes an antiferroelectric layer over a ferroelectric layer. The antiferroelectric layer, among other layers, can be tailored to customize the hysteresis loop shape, and the coercive electric field required to change polarization of the memory cell. Metal electrodes, and/or dielectric or metallic interlayers may also be employed to tailor the hysteresis. The memory cells can include FeRAMs or FeFETs. The memory cells provide a lower coercive electric field requirement compared to conventional ferroelectric memory cells, enhanced reliability, and require minimum changes to integrate into current integrated circuit fabrication processes.

Memory cell including polarization retention member(s) including antiferroelectric layer over ferroelectric layer

Disclosed is a threshold voltage-programmable field effect transistor-based (e.g., a ferro-electric field effect transistor (FeFET)-based) memory circuit employing source-line and/or bit-line-applied variable programming assist voltages. For single-bit data storage in a FeFET, decremental programming assist voltages are selectively applied by a voltage driver to the source-line and/or the bit-line connected to a FeFET during repeat programming processes when previous attempts at programming have failed. For multi-bit data storage in a FeFET, different programming assist voltages are associated with different multi-bit data values and at least one specific programming assist voltage is applied by a voltage driver to the source-line and/or the bit-line connected to a selected FeFET during a programming process to achieve storage of a specific multi-bit data value. Optionally, multiple FeFETs in the same row can be currently programmed with different multi-bit data values. Optionally, different decremental programming assist voltages are applied if/when repeat programming processes are required.

Memory circuits employing source-line and/or bit-line-applied variable programming assist voltages

The present invention relates to an integrated electronic circuit and method of making comprising a first transistor () and a ferroelectric capacitor (). The ferroelectric capacitor () comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor ().

Integrated electronic circuit and method of making comprising a first transistor and a ferroelectric capacitor

The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor.

Ferroelectric based transistors

The present invention relates to a voltage-controllable capacitor comprising a first electrode layer () composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (), a ferroelectric interlayer () having a thickness that is less than the thickness of the first electrode layer (), and a second electrode layer () composed of a non-ferroelectric material. The ferroelectric interlayer () is arranged between the first electrode layer () and the second electrode layer ().

Voltage-controllable capacitor comprising a ferroelectric layer and method for producing the voltage-controllable capacitor comprising a ferroelectric layer

The present invention relates to an integrated electronic circuit comprising a first transistor () and a ferroelectric capacitor (). The ferroelectric capacitor () comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor ().

Integrated electronic circuit comprising a first transistor and a ferroelectric capacitor

The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Complex circuit element and capacitor utilizing CMOS compatible antiferroelectric high-k materials

An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from the first line to a second line based on a capacitive coupling.

Integrated circuit, and method for transferring data

A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.

Method for classifying memory cells in an integrated circuit

A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold level is detected for each one of the memory cells of the first group only. The first group of memory cells is verified by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

Method for programming a block of memory cells, non-volatile memory device and memory card device

A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Memory device with adaptive sense unit and method of reading a cell array

A memory device () includes a memory array (). The memory array () has at least one memory area () that includes a plurality of conductive lines () and a plurality of memory cells () connected to the conductive lines (). The conductive lines () are arranged at positions (n) within the memory area (). The memory cells () are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (). The memory device () is constructed such that for programming of a memory cell () an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line () to which the memory cell () is connected.

Memory device and method for operating a memory device

A method for operating a semiconductor memory (M) including a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first side (S) and a second side (D), the memory cells (MC) are connected by a bitline (BL) on the first side (S) of the memory cell and connected by another bitline (BL) on the second side (D) of the memory cell, the first side (S) of a memory cell is connected to a same bitline (BL) as the second side (D) of an adjacent memory cell, each of the memory cells (MC) is connected by a same wordline (WL), including the steps of: selecting a memory cell (MC) for operation, applying a first potential (VS) to all the bitlines (BL) connected to memory cells (MC) arranged to the first side (S) of the memory cell, applying a second potential (VD) to all the bitlines (BL) connected to memory cells (MC) arranged to the second side (D) of the memory cell, and performing the desired operation on the memory cell (MC).

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Dresden, Germany

Konrad Seidel