Intel Corporation

Intel Corparation

Konrad K Lai

Ravi Rajwar

Martin Guy Dixon

Gurbir Singh

Matthew C Merten

Nitin V Sarangdhar

Bret L Toll

Peter Lachner

Laura A Knauth

Peter D MacWilliams

Michael W Rhodehamel

Wen-Hann Wang

Shih-Lien L Lu

Hong Wang

Ralph Michael Kling

Frederick J Pollack

Michael T Imel

Jih-Kwon Peir

Haitham H Akkary

Stephen S Pawlowski

Mingqiu Sun

Robert S Chappell

Scott H Robinson

Randy M Bonella

Matthew A Fisch

Mandar S Joshi

Donald B Alpert

Alexandre J Farcy

Michael A Kozuch

Kenneth D Shoemaker

Rajesh S Parthasarathy

Kevin C Kahn

Suresh Srinivas

Peggy J Irelan

Vijaykumar Balaram Kadgi

Yong-fong Lee

Ilhyun Kim

Uma Srinivasan

David A Berson

Stephen H Dohrmann

Prakash Math

Steve Y Zhang

Robert Riches

Glenford J Myers

Glenn J Hinton

Dinesh Somasekhar

James A Valerio

Beeman C Strong

Ofer Levy

Sunil R Shenoy

Ashwani Kumar Gupta

Tong Li

David L Budde

Larry O Smith

John M Bauer

Jeff J Baxter

Scott B Huck

Randy L Steck

Thomas F Toll

Thilo Schmitt

Thomas Toll

Glen Myers

Michael W Rodehamel

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Tracking mode of a processing device in instruction tracing systems

Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Instruction and logic to test transactional execution status

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Last branch record indicators for transactional memory

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code

Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.

Event counter checkpointing and restoring

Last branch record register for storing taken branch information and transactional memory transaction indicator to be used in transaction execution analysis

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.

Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment

Growing community of inventors

Vancouver, WA, United States of America

Konrad K Lai