Samsung Electronics Co., Ltd.

Kong-soo Cheong

Jong-hyon Ahn

Sung-Gun Kang

Ki-seog Youn

Jeong-Ho Shin

Deok-hyung Lee

Jin-Won Jun

Kyung-Soo Kim

Ki-Young Kim

Hee-Sung Kang

A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same

In a method of manufacturing a semiconductor device, a preliminary metal silicide layer is selectively formed on a substrate having a transistor, the transistor having source/drain regions. A capping layer having a thermal expansion coefficient greater than that of the preliminary metal silicide layer is formed on the substrate having the preliminary metal silicide layer. The substrate is thermally treated to form a metal silicide layer, and to apply a tensile stress caused by a thermal expansion coefficient difference between the metal silicide layer and the capping layer to the source/drain regions of the transistor.

Method of manufacturing semiconductor device

In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

Method of forming a metal gate in a semiconductor device

Trench isolation type semiconductor device which prevents a recess from being formed in a field region

In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.

Semiconductor device having MOS varactor and methods for fabricating the same

Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.

Method of forming thick metal silicide layer on gate electrode

In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.

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Seoul, South Korea

Kong-soo Cheong