Megamos Corporation

Magepower Semiconductor Corp.

Kong Chong So

Fwu-Iuan Hshieh

Danny Chi Nim

A new transistor cell is disclosed in this invention which is formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of the substrate. The DMOS cell includes a polysilicon layer constituting a gate supported on a top surface of the substrate, the gate surrounding and defining an outer boundary of the transistor cell having a removed polysilicon opening disposed substantially in a central portion of the cell. The DMOS cell further includes a source region of the first conductivity disposed in the substrate near edges of the removed polysilicon opening with a portion extends underneath the gate. The DMOS cell further includes a body region of a second conductivity type disposed in the substrate occupying an entire region under the removed polysilicon opening thus encompassing the source region and having a portion extends underneath the gate. The body region defining substantially a merged-double-U-shaped region including a left-U-shaped implant region and a right-U-shaped implant region and a merged region disposed substantially at a central portion under the removed polysilicon opening. In a preferred embodiment, the merged double-U-shaped region constituting the body region further includes a deep high concentration body dopant region and a shallow high concentration body dopant region.

DMOS transistors with diffusion merged body regions manufactured with

The invention discloses method for fabricating a MOSFET on a substrate to improve device ruggedness. The method includes steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and growing an initial oxide layer over the epi-layer; (b) applying an active mask for etching the active layer to define an active area followed by depositing an overlaying polysilicon layer and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the mask and carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) applying a source blocking mask for implanting a plurality of source regions in the body regions with ions of the first conductivity type followed by removing the blocking mask and a source diffusion process; (e) forming an overlying insulation layer covering the MOSFET followed by applying a contact mask to open a plurality of contact openings; (f) performing a low energy body-dopant and high energy body dopant implant to form a shallow high-concentration body dopant and a deep high-concentration body dopant region followed by applying a high temperature process for densification of the insulation layer and activating diffusion of the deep and shallow body dopant regions wherein the deep high-concentration body-dopant regions are formed below the source regions and extends beyond the contact regions but are kept at lateral distance away from a channel region of the MOSFET in the body region whereby device ruggedness is improved without increasing threshold voltage.

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San Jose, CA, United States of America

Kong Chong So