Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Kong-Beng Thei

Harry Chuang

Chien-Chih Chou

Yi-Huan Chen

Alexander Kalnitsky

Sheng-Chen Chung

Chiung-Han Yeh

Mong-Song Liang

Fu-Jier Fan

Hsiao-Chin Tuan

Yi-Sheng Chen

Harry-Hak-Lay Chuang

Ming-Yuan Wu

Chung Long Cheng

Szu-Hsien Liu

Chen-Liang Chu

Ta-Wei Lin

Chung-Long Cheng

Jung-Hui Kao

Su-Chen Lai

Ker-Hsiao Huo

Bao-Ru Young

Harry Hak-Lay Chuang

Lee-Wee Teo

Tzung-Chi Lee

Yu-Ying Hsu

Dun-Nian Yaung

Mong Song Liang

Jen-Cheng Liu

Meng-Han Lin

Shou-Gwo Wuu

Ta-Hsun Yeh

Hsing-Chih Lin

Ming-Ta Lei

Kuo-Reay Peng

Chun-Hon Chen

Yen-Shih Ho

Jhu-Min Song

Ssu-Pin Ma

Cheng-Yuan Tsai

Ping-Wei Wang

Hun-Jan Tao

Chun Lin Tsai

Yao-Wen Chang

Chun-Yi Lee

Fei-Yuh Chen

Shun-Jang Liao

Chung-Shi Liu

Chern-Yow Hsu

Ming Chyi Liu

Jiun-Lei Jerry Yu

Chien-Wen Chen

Shien-Yang Wu

Yi-Shien Mor

Yi-Min Chen

Wen-Huei Guo

Oscar M K Law

Jhih-Bin Chen

Ta-Yuan Kung

Hung-Chih Tsai

Ruey-Hsin Liu

Ryan Chia-Jen Chen

Chih-Chang Cheng

Chih-Tang Peng

Shyh-Chyi Wong

Chih-Wen Hsiung

Chih-Hsien Lin

Gwo-Yuh Shiau

Alex Kalnitsky

Fu-Hsiung Yang

Hsien-Wei Chen

Shin-Puu Jeng

Hao-Yi Tsai

Chung-Te Lin

Jin-Yuan Lee

Jhon-Jhy Liaw

Carlos H Diaz

Hung-Chang Hsieh

Hua-Tai Lin

Yu Chao Lin

Yi-Ming Sheu

Chu-Yun Fu

Tsung-Chieh Tsai

Gwan Sin Chang

Cheng-Cheng Kuo

Chih-Wen Yao

Chien-Wen Lai

Sheng-Yuan Lin

Chun-Lin Tsai

Hak-Lay Chuang

Chao-Hsuing Chen

Jian-Shiou Huang

Yuan-Chen Sun

Yi-Hsing Chen

Shwangming Jeng

Chin-Min Huang

Chia-Cheng Chang

Keh-Chiang Ku

Cherng-Shyan Tsay

Fei-Yun Chen

In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Recessed gate for an MV device

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate having an isolation ring extending in the direction substantially parallel to the surface of the substrate, an active region over the substrate and laterally enclosed by the isolation ring, a seal ring structure over the substrate, the seal ring structure laterally enclosing the active region and including at least a wiring layer and at least a via layer, and an encapsulant material laterally enclosing the seal ring structure.

Semiconductor structure and manufacturing method of the same

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Boundary design for high-voltage integration on HKMG technology

In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device

A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within

A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.

Semiconductor testing device and method of operating the same

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Semiconductor structure and method of forming thereof

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

FUSI gated device formation

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments extending in parallel along the first direction; and a protection structure over the substrate and at least partially overlaps the gate electrode.

A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.

Semiconductor device and manufacturing method of the same

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.

Through silicon via design for stacking integrated circuits

Growing community of inventors

Hsin-Chu, Taiwan

Kong-Beng Thei