Freescale Semiconductor,inc.

Kong Bee Tiu

Wai Yew Lo

Fuaida Harun

Ruzaini B Ibrahim

Azhar Aripin

Chee Seng Foong

Lan Chu Tan

Teck Beng Lau

Cheng Choi Yong

Wen Shi Koh

Lau Teck Beng

Chiaw Mong Chan

Soo San Yong

A semiconductor device includes a lead frame, and an integrated circuit die. The lead frame has a flag for supporting the die and leads that surround that flag and die. The lead frame also has ground ring that surrounds the flag and die. First bond wires electrically connect the die to the lead frame leads. An insulating layer is disposed on the ground ring, and a power layer is disposed on the insulating layer. The semiconductor device further includes second bond wires that connect the die to the ground ring and third bond wires that connect the die to the power layer.

Semiconductor device with combined power and ground ring structure

A semiconductor package includes a lead frame having an interior region and leads surrounding the interior region, an integrated circuit, a region of insulating material, and a power bar. The integrated circuit, which is disposed in the interior region, has bond pads and electrical couplings (e.g., bond wires) between the bond pads and the leads. The region of insulating material is disposed on at least some of the lead frame leads and the power bar is disposed on the region of insulating material. There also are electrical couplings between the power bar and at least some of the bond pads.

Semiconductor package with lead mounted power bar

A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.

Multi-die sensor device

A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.

Quad flat semiconductor device with additional contacts

An improved method of bonding an insulated wire () that has one end connected to a first bond pad () to a second bond pad () includes moving a tip of a capillary () holding the bond wire () over the surface of the second bond pad () such that the bond wire () is rubbed between the capillary tip () and the second bond pad (), which tears the bond wire insulation so that at least a portion of a metal core of the wire () contacts the second bond pad (). The wire () is then bonded to the second pad () using thermocompression bonding. The tip of the capillary () is roughened to enhance the tearing of the bond wire insulation.

Wirebonding insulated wire and capillary therefor

A stacked multichip package () has a base carrier () having a top side () and a bottom side (), a bottom integrated circuit die () having a bottom surface () attached to the base carrier top side (), and an opposing, top surface (). The top surface () has a peripheral area including a plurality of first bonding pads and a central area (). A bead () is formed on the top surface () of the bottom die () between the peripheral area and the central area (). A top integrated circuit die () having a bottom surface is positioned over the bottom die () and the bottom surface of the top die () is attached to the top surface () of the bottom die () via the bead (). The bead () maintains a predetermined spacing between the bottom die () and the top die () so that wirebonds of first wires () connecting the bottom die () to the base carrier () are not damaged when the top die () is attached to the bottom die ().

Stacked die semiconductor device

A method of forming a substrateless semiconductor package () includes forming a carrier () on a base plate () and attaching an integrated circuit (IC) die () to the carrier (). The IC die () then is electrically connected to the carrier (). A molding operation is performed to encapsulate the IC die (), the electrical connections () and the carrier (). Thereafter, the base plate () is removed.

Method of forming a substrateless semiconductor package

An electrical connection for connecting a bond pad of a first device and a bond pad of a second device with an insulated or coated wire. The electrical connection includes a first wirebond securing a first portion of the insulated bond wire to the first device bond pad. A second wirebond secures a second portion of the insulated bond wire to the second device bond pad. A bump is formed over the second wirebond, and the bump is offset from the second wirebond. The offset bump enhances the second bond, providing it with increased wire peel strength.

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Port Klang, Malaysia

Kong Bee Tiu