Seagate Technology Incorporated

Lsi Corporation

Komal Shah

Ramesh C Tekumalla

Priyesh Kumar

Sachin Bastimane

Jay Shah

Bharat P Londhe

Partho Tapan Chaudhuri

Paras Gangwal

Deep Neema

Surbhi Bansal

A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

Programmable scan chain debug technique

In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.

Circuit including efficient clocking for testing memory interface

An on-chip clock (OCC) circuit of an integrated circuit includes a clock generator, an OCC controller, and an OCC observation circuit. The clock generator is configured to generate a plurality of clock signals. The OCC controller is configured to receive the clock signals and generate an OCC output for use by the scan chains of logic blocks. The OCC observation circuit is configured to generate a status output on a status output port based on the OCC output during an at-speed capture phase and a scan enable signal. Patterns of the status output with respect to the scan enable signal include a valid pattern indicating that the OCC output includes a valid number of at-speed capture pulses, a first invalid pattern indicating a first error in the OCC output, and a second invalid pattern indicating a second error in the OCC output that is different from the first error.

On-chip clock control monitoring

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic.

At-speed scan testing of clock divider logic in a clock module of an integrated circuit

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.

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Mumbai, India

Komal Shah