Fujitsu Corporation

Koki Yamagata

Takahiro Suzuki

Hiroyasu Nakagawa

Yuuitsu Ogata

Fusako Ishino

Noriyoshi Takahashi

A base station device uses a first card as an M2M card, second cards as general cards, and a third card as a spare card from among call process cards included in a signal processing unit. A call control unit allocates, to the M2M card, a call that is received from an M2M terminal and in which the service type determined by a service type determination unit is an M2M service. Furthermore, the call control unit allocates, to a general card, a call that is received from a general terminal and in which the service type determined by service type determination unit is a general service.

Base station device

A method for controlling an interrupt from a peripheral device to a processor, the peripheral device including at least an interrupt control unit, an interrupt request level holding unit, and an interrupt vector holding unit, which includes the steps of: a) updating the contents of the interrupt request level holding unit in accordance with commands in a software sent from an external device, for example, a subprocessor; b) updating the contents of the interrupt vector holding unit in accordance with commands in the software sent from the external device; c) reading an interrupt request level from the interrupt request level holding unit to the interrupt control unit; d) issuing the interrupt request level from the interrupt control unit to the processor when the peripheral device performs the interrupt operation; e) performing various processes and asserting the results of the signal processes from the processor to the peripheral device; f) reading an interrupt vector from the interrupt vector holding unit to the interrupt control unit, and setting a vector number to lower byte of data to assert data and a size acknowledgment; g) notifying the interrupt vector from the interrupt control unit to the processor; i) latching the vector number and negating address and data strobes in the processor; k) negating the data and the size acknowledge in the interrupt control unit; and l) starting the next cycle of the interrupt operation in said processor.

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Sendai, Japan

Koki Yamagata