Hitachi, Ltd.

Koki Tsutsumida

Hideki Hayashi

Kozaburo Kurita

Koichi Sugimoto

Shigeru Nakahara

Yuko Ito

Yasuhiro Fujimura

Hideki Sakakibara

Masatoshi Kawashima

Tomoji Nakamura

Tsutomu Sato

Yuichi Ito

Yasuyoshi Sunaga

Atsushi Hazeyama

Kenichi Tada

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S) and a predetermined linearity condition (S).

Semiconductor integrated circuit

A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit.

Semiconductor device

A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.

Semiconductor integrated circuit device for scan testing

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Ome, Japan

Koki Tsutsumida