Renesas Electronics Corporation

Koki Tsurusaki

Satoshi Shibatani

An object of the present invention is to largely reduce a period required for a layout design of a semiconductor integrated circuit device by simplifying a hierarchical layout process. It is necessary to couple a signal line between a circuit belonging to a top and a signal terminal of a block, and there is such an inadequate situation that the signal line cannot be coupled to a predetermined location of the signal terminal of the block or the signal line needs to be largely detoured depending on congestion conditions of the other signal lines in the block and the signal lines of the top coupled to the other blocks. Accordingly, location information of the signal terminal is deleted before the signal line is coupled, so that the signal line can be coupled irrespective of the location information of the signal terminal of the block. Further, the signal line can be optimally coupled in some cases by arranging the circuit of the top on the inner side relative to a boundary of the block, so that location information of the boundary of the block as well as the location information of the signal terminal is deleted.

Growing community of inventors

Tokyo, Japan

Koki Tsurusaki