Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Koki Noguchi

Toru Baji

Shiro Baba

Yasushi Akao

Atsushi Kiuchi

Yuji Hatano

Masashi Horiguchi

Asao Nishimura

Masaharu Kubo

Kazuyoshi Shiba

Toshio Miyamoto

Hiroshi Ohsuga

Hironobu Hasegawa

Satoshi Michishita

Nobukazu Kondo

Ikuya Kawasaki

Tetsuya Nakagawa

Yasuhiro Sagesaka

Shinichi Yoshioka

Tomohisa Kohiyama

Akifumi Tsukimori

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core () integrated as a single bus master, an integrated external bus interface () and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Terminal apparatus

A built-in memory is divided into the following two types: first memoriesandand second memoriesand, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU corecan simultaneously transfer two data values from the built-in memory to a DSP engine. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU corecan access an external memory in parallel with the access to the second memoriesandand the first memoriesand

Microcomputer

Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Semiconductor device

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS, WHEREIN ELECTRODES OF THE SEMICONDUCTOR CHIPS ARE ELECTRICALLY CONNECTED TOGETHER VIA WIRING SUBSTRATES OF THE SEMICONDUCTOR CHIPS

In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

Data processing device having a central processing unit and digital signal processing unit

An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.

Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system

For improving data efficiency of a bus in a system using address/data multiplex bus, in a processor for information processing equipment, there are provided buffers which store plural sets of write addresses and data for a system bus, a comparator for deciding whether write addresses in succession forming a continuous write address exist in the write addresses stored in the buffers, and apparatus for converting access corresponding to writing operations for the continuous write addresses into a fixed length burst transfer protocol which can be transferred with a series of continuing data cycles following one address cycle, when the comparator 27 decides that write addresses in succession exist.

Method and apparatus for converting non-burst write cycles to burst write cycles across a bus bridge

A semiconductor device including a port circuit ( ) connected to an internal circuit, external terminals to which the port circuit is connected and a boundary scanning circuit ( ), the boundary scanning circuit being the one that makes access to the external terminals through the test access terminals. The test access terminals are also used as predetermined external terminals among the external terminals. Selection means ( to ) are provided for selectively determining whether the multi-use terminals (P to P ) be connected to the port circuit or to the boundary scanning circuit, and for selecting, as an initial state, the state where the multi-use terminals are connected to the boundary scanning circuit in response to the power-on reset. Since the test access terminals need not be dedicated, the boundary scanning function can be furnished while guaranteeing pin compatibility of external terminals. When the boundary scanning function is not utilized or when the port function of the multi-use terminals is not used despite of using the boundary scanning function, complete compatibility is guaranteed for the semiconductor device which is not furnished with the boundary scanning function.

A circuit includes a transmission function of transmitting data together with a source clock synchronized to the data to another module, a reception circuit for receiving the data outputted by the module and a source clock synchronized to the data, and a synchronization circuit for connecting the circuit having a transmission function to the reception circuit are formed on a single-chip integrated circuit. Even if the module connected to the bus is changed, i.e., even if the operation clock frequency of the module of the other party is changed, other modules can be used as they are without making any change. The cost needed at the time of system construction can thus be reduced. Furthermore, as for the aspect of performance, only one synchronization circuit is needed. The increase of latency caused by synchronization can also be suppressed to the minimum.

Information processing apparatus

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core ( ) integrated as a single bus master, an integrated external bus interface ( ) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Growing community of inventors

Tokyo, Japan

Koki Noguchi