Fujitsu Corporation

Koken Shimizuno

Hiroyuki Kojima

Naoya Ishimura

A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.

Cache memory control device and pipeline control method

A cache memory control circuit allowing an MIB to have information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is valid or not includes: a first determination section (step S) that determines whether an index and upper address section of the request address related to the move-in request and those of the request address that is related to a preceding move-in request and has been registered in the MIB do not correspond respectively to each other, a third determination section (step S) that determines whether an index and upper address section in the address related to the move-in request and those in the replace address that is related to the preceding move-in request and has been registered in the MIB do not correspond respectively to each other; and a tag search section (step S) that continues the processing for the move-in request in the case where an affirmative result has been obtained both in the first and third determination sections and the replace destination is valid.

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Kawasaki, Japan

Koken Shimizuno