Iqm Finland Oy

Kok Wai Chan

Tianyi Li

Wei Liu

Kuan Yen Tan

Caspar Ockeloen-Korppi

Manjunath Ramachandrappa Venkatesh

Hasnain Ahmad

Mikko Möttönen

Jan Goetz

Máté Jenei

Juha Hassel

Johannes Heinsoo

Lily Yang

Jean-Luc Orgiazzi

Alessandro Landra

Mario Palma

Vasilii Sevriuk

Tiina Naaranoja

Jari Penttilä

A method, system, and arrangement for resetting qubits are disclosed. An example system includes one or more quantum circuit refrigerators for resetting qubits. Each of the quantum circuit refrigerators includes a tunneling junction and a control input for receiving a control signal. Photon-assisted single-electron tunneling takes place across the respective tunneling junction in response to a control signal. Capacitive or inductive coupling elements between the qubits and the quantum circuit refrigerators couple each qubit to the quantum circuit refrigerator(s). The qubits, quantum circuit refrigerators, and coupling elements are located in a cryogenically cooled environment. A common control signal line to the control inputs crosses into the cryogenically cooled environment from a room temperature environment.

Method and arrangement for resetting qubits

The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.

Electroplating for vertical interconnections

The invention relates to the field of chip fabrication, in particular to the fabrication of superconducting integrated circuits for use in quantum computers. Raised and recessed alignment structures are provided on the surfaces of two substrate such that the raised and recessed alignment structure extends within the recessed alignment structure to a maximum depth determined by the geometry of the alignment structures. The alignment structures act as a hard stop for positioning and aligning the substrates for flip chip bonding.

Chip fabrication method and product including raised and recessed alignment structures

A sample cell is provided for holding a sample to be placed in a cryogenically cooled environment. The sample cell comprises an airtight, openable and closable enclosure. Within said enclosure is a sample base for receiving the sample. A refrigerator attachment is provided for attaching the sample cell to a refrigerated body of a cryogenically cooled environment. The sample cell comprises a thermal connection between the sample base and the refrigerator attachment. One or more airtight connectors are provided for establishing electric connections between inside and outside of said enclosure.

Sample cell for handling and measuring sensitive samples in low temperature conditions

A three-dimensional superconducting qubit and a method for manufacturing the same are disclosed. In an example, a three-dimensional superconducting qubit comprises a structural base comprising one or more insulating materials, and superconductive patterns on surfaces of the structural base. The superconductive patterns form at least a capacitive part and an inductive part of the three-dimensional superconducting qubit. A first surface of the surfaces of the structural base defines a first plane and a second surface of the surfaces of the structural base defines a second plane, the second plane being oriented differently than the first plane. At least one superconductive pattern of the superconductive patterns extends from the first surface to the second surface.

Three-dimensional superconducting qubit and a method for manufacturing the same

This disclosure describes a superconducting device comprising a trench and a cavity that extends through a superconducting base layer. The trench crosses the cavity. The superconducting device further comprises a first junction layer that extends from a first region of the superconducting base layer to the cavity, an insulating layer on the surface of the first junction layer, and a second junction layer that extends from a second region of the superconducting base layer to the cavity. The second junction layer overlaps with the insulating layer on the bottom of the cavity. The disclosure also describes a method for producing this disclosed superconducting device.

Superconducting device

The present invention relates to the manufacture of Josephson junctions. Such Josephson junctions may be suitable for use in qubits. High-quality, potentially monocrystalline, electrode and dielectric layers are formed using blanket deposition. Subsequently, the structure of one of more Josephson junctions is formed using multi-photon lithography to create openings in a resist followed by etching the electrode and dielectric layers.

Method for manufacturing Josephson junctions

An airbridge implements connections on a superconducting chip. It comprises a strip of superconductive material between a first superconductive area and a second superconductive area. A first end of said strip comprises a first planar end portion attached to and parallel with said first superconductive area, and a second end of said strip comprises a respective second planar end portion. A middle portion is located between said first and second planar end portions, forming a bend away from a plane defined by the surfaces of the first and second superconductive areas. First and second separation lines separate the end portions from the middle portion. At least one of said first and second separation lines is directed otherwise than transversally across said strip.

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Espoo, Finland

Kok Wai Chan