Silanna Asia Pte Ltd

Lite-on Technology Corporation

Avago Technologies Ecbu IP (singapore) Pte. Ltd.

02 Micro International Limited

Kok Soon Yeo

Rawinder Dharmalinggam

John Julius Asuncion

Lian Chun Xu

Kais Badami

Chee Keong Teo

Wai Keat Tai

Ai Min Xu

Hong Meng Joel Tang

Wai Keat Tal

During a first mode of operation, a zero current detect (ZCD) signal is asserted in response to detecting a zero current condition at a switch node of a power converter. The power converter enters a light load mode of operation when the ZCD signal is asserted between a beginning point and a trigger point of a period of a PWM signal. A compensator voltage is generated based on a feedback voltage indicative of an output voltage. The compensator voltage is compared to a threshold voltage that represents a limit for the compensator voltage during the light load mode of operation determined over a range of the output voltage. The power converter exits the light load mode back to the first mode of operation in response to the compensator voltage being beyond the threshold voltage.

Light load mode entry or exit for power converter

An optical receiver has a voltage supply, a first node, and a second node. A first input of a differential amplifier is coupled to the first node and a second input of the differential amplifier is coupled to the second node. A photodetector is coupled between the voltage supply and the first node, which produces a photodetector capacitance. A programmable variable capacitor having a capacitance selectively matched to the photodetector capacitance is coupled between the voltage supply and the second node.

Optical receiver with matched photodetector capacitance

A circuit has a voltage source, a node, a photodetector electrically coupled between the voltage source and the node, a resistor electrically coupled between the node and ground, and a voltage clamp electrically connected to the node, the voltage clamp configured to maintain a reverse bias of the photodetector above a predetermined level.

Photodiode circuit with improved response time

A compensating circuit for providing a compensating control signal to a regulating circuit is provided. The compensating circuit includes a multiplying circuit and a miller capacitor. The multiplying circuit may provide a predetermined multiplication factor to a miller current level based on a resistor ratio. The multiplying circuit may also provide a voltage gain stage before the miller capacitor. Both multiplying circuits enable the size of the miller capacitor to be reduced resulting in valuable printed circuit board space savings.

Compensating capacitive multiplier

Growing community of inventors

Singapore, Singapore

Kok Soon Yeo