Infineon Technologies Ag

Infineon Technologies Austria Ag

Kok Kiat Koo

Carlo Marbella

Ganesh Vetrivel Periasamy

Christian Arndt

Woon Yik Yong

Ai Min Tan

Edward Myers

Balehithlu Manjappaiah Upendra

Upendra Balehithlu Manjappaiah

Khai Seen Yong

A semiconductor package includes a first semiconductor die, a first group of leads that each comprise an interior end, and an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interior ends of the leads from the first group, wherein a gap is disposed between outer sidewalls of two immediately adjacent ones of the leads from the first group, wherein the first semiconductor die is mounted on the first group of leads such that a lower surface of the first semiconductor die faces and overlaps with each of the leads from the first group, and wherein the lower surface of the first semiconductor die extends across the gap between outer sidewalls of two immediately adjacent ones of the leads from the first group.

Semiconductor package and lead frame with enhanced device isolation

A test probe for testing a chip package is provided, wherein the test probe comprises a test probe body comprising a conductive material; and a probe tip arranged on an end of the test probe body and comprising carbon nano tubes.

Test probe and method of manufacturing a test probe

A semiconductor device includes a first contact element, a second contact element, a semiconductor chip, and an encapsulation material. The first contact element is on a first side of the semiconductor device. The second contact element is on a second side of the semiconductor device opposite to the first side. The semiconductor chip is electrically coupled to the first contact element and the second contact element. The encapsulation material encapsulates the semiconductor chip and portions of the first contact element and the second contact element. The encapsulation material defines at least two notches on a third side of the semiconductor device extending between the first side and the second side.

Semiconductor device including an encapsulation material defining notches

A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

System and method for an electronic package with a fail-open mechanism

In accordance with an embodiment, a semiconductor package includes a first surface configured to be mounted on a circuit board, and a region of thermally expandable material configured to push the first surface of the semiconductor package away from the circuit board when a temperature of the thermally expandable material exceeds a first temperature.

Growing community of inventors

Singapore, Singapore

Kok Kiat Koo