Seiko Instruments Inc

Koju Nonaka

Kenji Kitamura

Yutaka Saito

Masaaki Kamiya

Hitomi Watanabe

Takao Akiba

Shigeyuki Tsunoda

The present invention is provided for improving latch-up resistance in a semiconductor integrated circuit device employing CMOS structure, for preventing the photoelectric carriers from getting into the sensors and improving the afterimage characteristic in a semiconductor image sensor device, and for impurity the switching characteristic in a semiconductor device having bipolar element. An electron beam of over 2 MeV and 1E15/cm.sup.2 is irradiated to a monocrystal silicon semiconductor region in a substrate and then annealing is performed at a high temperature of over 200.degree. C. As a result, at 150 K., a shallow level traps of which the activation energy from a valence band EV is under 0.1 eV and which is produced at the concentration of about 1.2-1.7E15/cm.sup.3, and a deep level traps of which the activation energy is 0.28-0.32 eV and which is produced at the concentration of about 1.6-2.0E13/cm.sup.3 are obtained. Then a semiconductor substrate having both the level traps stated above as recombination centers in a band gap of silicon is obtained. The chip size of this semiconductor substrate doesn't increase, and furthermore the cost of it is low as an epi wafer is not used. As well, it is possible to manufacture a semiconductor integrated circuit device just before or just after a process step of evaluating the electrical characteristic of a semiconductor integrated circuit device.

Semiconductor device having defects of deep level generated by electron

The semiconductor device contains a CMOS transistor pair comprised of a P channel MOS transistor having a polysilicon gate 4 and an N channel MOS transistor having a polysilicon gate. The MOS transistor has a channel dope layer 5 localized in a vicinity of a surface of a channel region just below a gate electrode. This channel dope layer 5 has a quite shallow p-n junction depth xj effective to suppress a leak current. Thereby, an amount of impurity concentration in the surface of the channel region can be reduced to improve a subthreshold characteristics of the MOS transistor and to enable a low voltage and high speed operation under suppressing a leakage current.

Semiconductor device

Growing community of inventors

Tokyo, Japan

Koju Nonaka