Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Semiconductor Limited

Koju Aoki

Hiroyuki Sakima

Koji Takekawa

Takahiro Watai

Masaya Mizutani

Kazuhiko Kobayashi

Hirohisa Matsuki

Mitsutaka Sato

Hideharu Sakoda

Katsuya Shimizu

Kazuhiro Tomita

Osamu Igawa

Masahiro Tsukahara

Katashi Hasegawa

Takuya Okajima

Takaoki Ogawa

Hiroshi Baba

A method and circuit for preventing an output signal, which has been corrected through digital correction or analog correction, from deviating from a target value and for preventing power supply noise and power consumption from increasing. A sensor amplification circuit receives output of a sensor as an input signal. Correction points are set at predetermined temperature intervals. The sensor amplification circuit performs digital correction for correcting the input signal with correction data set for each correction point. Further, the sensor amplification circuit performs a second correction for correcting the input signal between the correction points with gradient data calculated from the correction data for two of the correction points that are adjacent to each other.

Method and circuit for correcting sensor temperature dependency characteristic

An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode. A MOS type variable capacitance device capable of obtaining a characteristic of good linearity for a wide range relative to the inter-terminal voltage VT and capable of coping with the improvement of the performance of a VCO circuit, etc., as well as simple in the structure, and capable of being manufactured easily with no requirement for addition of masks and steps can be provided.

MOS type variable capacitance device

A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive capacities, a second amplification circuit, which has four series-connected inverter circuits, and a feedback circuit. One of the inverter circuits is connected between a capacitor and an inverter circuit via a first switch circuit and a second switch circuit. This varies the drive capacity of the first amplification circuit. The feedback circuit functions as a variable resistor having two transistors.

Prescaler and buffer

An amplifier circuit which is connected to a sensor and variably sets an amplification property and a control method thereof are disclosed, the circuit having the capability of restricting the influence of change with time and temperature change. The amplifier circuit, which receives, as an input, a detection signal from the sensor and variably sets an amplification property, comprises: (1) a first reference value retaining unitfor retaining a first reference value Kfor setting an amplification property which makes an output signal be a specified detection reference output voltage when a reference input condition KJ is detected; (2) a correction signal generation unitfor generating a correction signal HS which reduces the difference between an amplification property actual measurement value and an amplification property set value; and (3) a first amplification property correction unitfor correcting the first reference value Kbased on the correction signal HS.

Amplifier circuit and control method thereof

Provided are two monitor circuits for monitoring two input signals of an input stage differential amplifier, respectively, and two monitor circuit for monitoring two output signals of the input stage differential amplifier, respectively. When failure occurs at the bridge circuit of a sensor element or at the input stage differential amplifier, the monitoring units or the monitoring units detect abnormality, which makes it possible to detect the failure of the sensor element or the input stage differential amplifier. Therefore it is possible to detect failure such as a disconnection or a short circuit of the bridge circuit of the sensor element and failure which has occurred at the amplifier for amplifying outputs of the sensor element.

Sensor detection apparatus and sensor

The present invention realizes a miniaturized electronic device that is still capable of maintaining its high reliability even when miniaturized. To this end, the electronic device has an electronic circuit, comprising: a substrate with a circuit formation surface on which one part of the electronic circuit is formed; a polyimide layer that is formed on the circuit formation surface; and a spiral inductor constituting another part of the electronic circuit, which is formed into a pattern on the polyimide layer.

Electronic device

A method of switching the mode of a PLL circuit which has a high-speed mode and a normal mode, which allows the PLL circuit to be locked up at a high speed. The PLL circuit includes a phase comparator and a charge pump for generating a current depending on a comparison output signal from the phase comparator. The mode switching method includes the steps of detecting whether a current output terminal of the charge pump is in a high impedance state, and switching the mode of the PLL circuit from the high-speed mode to the normal mode or from the normal mode to the high-speed mode when the high impedance state is detected.

Mode switching method for PLL circuit and mode control circuit for PLL circuit

A reset circuit for a PLL frequency synthesizer allows the PLL to quickly generate an output signal after waking up from a power-save mode. The reset circuit includes a delay circuit for receiving a shift signal and generating the output signal by delaying the shift signal for a predetermined time. A determination signal receives the shift signal and the output signal, determines whether they match, and generates a reset signal from the predetermined time when the shift signal is being shifted. A control circuit receives a power-save signal, which deactivates the PLL, and provides the delay circuit with a control signal for matching the output signal with the shift signal when the power-save signal is cancelled.

Reset circuit and pll frequency synthesizer

A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.

Mode control of PLL circuit

A phase shifter that may be used in a quadrature modulator or an image suppression mixer. The phase shifter includes a low pass filter that receives an input signal and generates a first carrier signal. A high pass filter also receives the input signal and generates a second carrier signal. A phase difference detection circuit connected to the high and low pass filters receives the first and second carrier signals and generates a control signal based on the phase difference between the carrier signals. The control signal is fed back to at least one of the low pass filter and the high pass filter to compensate for phase errors caused by parasitic capacitance. The phase shifter has a small circuit area and is very accurate, allowing it to be used in communications devices.

Growing community of inventors

Kasugai, Japan

Koju Aoki