Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kojiro Suzuki

Keiri Nakanishi

Kohei Oikawa

Sho Kodama

Masahiro Takagi

Hiroshi Tsurumi

Koji Horisaki

Takashi Nakada

Masashi Jobashi

Yasuo Akatsuka

Kazuki Inoue

Toshihiro Nakamura

Kosuke Hatsuda

Tadahiro Kuroda

Youhei Fukazawa

Fumitoshi Hatori

Shuou Nomura

Yukimasa Miyamoto

Katsuyuki Nomura

Shinji Mita

Fuyuki Ichiba

Harutaka Goto

A display apparatus includes a plurality of surfaces, and a display device provided on at least one surface among the plurality of surfaces. A plurality of communication sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces and configured to perform communication within a predetermined distance, each of the plurality of communication sections including different identification information. A control section is configured to perform control of the plurality of communication sections and the display device. When another display apparatus is connected to the display apparatus, the control section periodically performs time synchronization to synchronize an image displayed on the display device with an image displayed on a display device provided in the other display apparatus.

Display apparatus and display system

According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit generates first compressed data and second compressed data by compressing first data and second data. The padding processing unit pads first padding data for the first compressed data in accordance with a first padding pattern and pads second padding data for the second compressed data in accordance with a second padding pattern.

Memory controller, method of controlling nonvolatile memory and memory system

According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.

Storage control device, storage system, and storage control method

According to an embodiment, a display block is a display apparatus including a plurality of surfaces. The display block includes a display device, a plurality of transmitting/receiving sections that perform communication within a predetermined distance, and a control section. The display device is provided on at least one surface of the plurality of surfaces. The plurality of transmitting/receiving sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces. The control section performs control of the plurality of transmitting/receiving sections and the display device.

According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit compresses first data to be written into a first page and second data to be written into a second page. The padding processing unit performs a padding processing such that the compressed first data is written into first memory cells, first padding data is written into second memory cells, the compressed second data is written into third memory cells, and second padding data is written into fourth memory cells.

Memory controller with data compression and padding features, method of controlling nonvolatile memory and memory system

According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.

Semiconductor apparatus, routing module, and control method of semiconductor apparatus

With a video compression device configured to compress one pixel per cycle, a predictive pixel generation unit generates predictive pixel values of a plurality of predictive modes defined assuming local decode pixels read from predetermined positions of a line memory as upper reference pixels and an input original image pixel positioned on the left side of a pixel to be compressed as a left reference pixel for the pixel to be compressed. A predictive mode determination unit calculates a predictive error in a unit based on differential values between the pixel value to be compressed and the predictive pixel value, and selects a minimum predictive mode. A DPCM unit generates a minimum differential value between the minimum predictive pixel value and the pixel to be compressed assuming local decode pixels as upper reference pixels and a local decode pixel value one cycle before as a left reference pixel.

Video compression device

A variable-length code decoding apparatus has a first-table storing part to store a first table, a second-table storing part to store a second table, a priority determining part to read out by priority a combination of zero information that is stored in the second table and corresponds a combination of variable-length codes having the largest number of codes, whereas if variable-length codes included in the input bitstream is not stored in the second table but stored in the first table, to read out zero information, and a decoding part to generate the decoded data based on the zero information or the combination of zero information read out by the priority determining part.

Variable-length code decoding apparatus, decoding system, and variable-length code decoding method

According to an embodiment of the invention, there is provided an image decoder for decoding encoded image data in an image block unit, including: a storage device configured to store a DC component of a past image block coefficient as a prediction value; a predict circuit configured to predict a DC component of a current image block coefficient using the prediction value; an inversely quantizing circuit configured to inversely quantize an image block coefficient outputted from the predict circuit; and a saturation processing circuit to execute a saturation processing of an image block coefficient outputted from the inversely quantizing circuit. A DC component of the image block coefficient outputted from the inversely quantizing circuit and a DC component of the image block coefficient after execution of the saturation processing are respectively inputted to the storage device.

Image decoder, image decoding method and computer program product for the same

A decoder configured to receive a variable length code stream packed in a fixed length area, and to execute variable length decoding and depacking of the variable length code stream, includes a first bit position table configured to store bit position data of the variable length code stream at a point where the variable length decoding is suspended. A bit length calculator is configured to calculate a bit length of variable length code stream remaining in the fixed length area after suspending the variable length decoding in the depacking, based on the bit position data.

Decoder and decoding method

A coded image data decoding system is designed to depack and variable-length decode image data packed by an image compressing/decompressing format wherein the sum of the length of components other than variable-length code components in one block and the length of an end code is not shorter than a bit length obtained by subtracting 1 bit from the number of bits of the maximum length of variable-length code words. This decoding system comprises: a main memory for storing code strings for one video segment; a decoding circuit for variable-length decoding code strings outputted from the main memory; a block storing circuit, provided between the main memory and the decoding circuit so as to be capable of storing code strings for one block, for storing code strings for concatenated two blocks; and a depacking circuit, including the block storing circuit, for suitably combining required portions of sequentially supplied code strings to complete code strings for one block when code strings supplied from the main memory are not code strings for one block.

System for decoding packed coded image data while depacking same

An object of the present invention to provide a pulse width modulation waveform generating circuit that it is possible to reduce circuit size and power consumption. A pulse width modulation waveform generating circuit comprises a ring oscillator having 64 pieces of inverters connected in series, inverters connected to output terminals of odd numbered stages of inverters in the ring oscillator, a multiplexer, a change detecting circuit, and an RS flip-flop. The multiplexer is supplied with output signals of even numbered stages of the inverters in the ring oscillator and output signal of the inverter. One of their signals is selected in accordance with logic of a digital signal. The RS flip-flop is set at time an edge detecting pulse is outputted from the change detecting circuit, and is reset at time an edge detecting pulse is outputted from the change detecting circuit.

Pulse width modulation waveform generating circuit

A driving voltage supplied to a semiconductor integrated circuit can be controlled. The semiconductor integrated circuit device provided with a voltage converter circuit comprises: a buffer circuit having: a P-channel MOS transistor having a source connected to a first supply voltage; and an N-channel MOS transistor having a source connected to a second supply voltage and a drain connected to a drain of the P-channel MOS transistor, an output voltage being outputted from a common-connected drain terminals of the two MOS transistors; a duty ratio control circuit having: a counter for outputting a first n-bit signal by repeatedly counting up numbers from 0 to (2.sup.n -1) one by one in synchronism with a first clock signal; and a comparator circuit for comparing the first n-bit signal with a second n-bit signal applied from the outside, and for outputting a first control signal to a gate of the P-channel MOS transistor and a second control signal to the N-channel MOS transistor; and a smoothing circuit for smoothing the output of the buffer circuit, a voltage smoothed by the smoothing circuit being outputted as an output of the voltage converter circuit.

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Kawasaki, Japan

Kojiro Suzuki