Kioxia Corporation

Toshiba Memory Corporation

Kojiro Shimizu

Kazuhiro Nojima

Masaki Tsuji

Hanae Ishihara

Yumiko Miyano

Naoki Yamamoto

Shunpei Takeshita

Rikito Kanazawa

A semiconductor device includes a body including conductive layers stacked and spaced from each other in a first direction and first and second areas along a second direction intersecting the first direction, an insulating portion extending along the directions in the areas and dividing the conductive layers in a third direction intersecting the directions, first columnar portions extending along the first direction in the first area and including a semiconductor layer, memory cells being formed at intersections between the conductive and semiconductor layers, second columnar portions extending along the first direction in the second area and including an insulator, third columnar portions extending along the first direction in the second area and including a semiconductor layer, and contacts extending along the first direction in the second area and connected to a conductive layer. The second portions are arranged along the insulating portion on both sides thereof in the third direction.

Semiconductor device and manufacturing method thereof

According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

Semiconductor memory device

A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layersand a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CPwhich extends in the second area in the first direction and is connected to the logic circuit.

Semiconductor storage device and method of manufacturing the same

A manufacturing method of a semiconductor memory device in an embodiment, includes: forming a first mask pattern having a first opening and a plurality of second openings above a stacked body; forming a second mask pattern covering some of the plurality of second openings; and etching the stacked body with the first mask pattern as a mask while sequentially exposing the plurality of second openings by causing an end of the second mask pattern to retreat to form a first hole extending in the stacked body in a stacking direction of the stacked body at a position of the first opening and form a plurality of second holes extending in the stacked body to different depths in the stacking direction at positions of the plurality of second openings, and reaching first layers of a plurality of first layers at different levels.

Manufacturing method of semiconductor memory device and semiconductor memory device

According to one embodiment, a semiconductor memory device includes: first interconnect layers; a second interconnect layer separate from the first interconnect layers; a third interconnect layer separate from the first interconnect layers and adjacent to the second interconnect layer in a second direction; a first memory pillar which passes through the second interconnect layer; a second memory pillar which passes through the third interconnect layer. The second interconnect layer includes a first portion connected to a first contact plug. The third interconnect layer includes a second portion connected to a second contact plug. The first and second portions are arranged along a third direction which intersects the second direction.

A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layersand a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CPwhich extends in the second area in the first direction and is connected to the logic circuit.

A semiconductor device according to an embodiment includes a first contact electrically connected to a first conductive layer with a diameter size smaller than a diameter size of a first support pillar at a region position on an inner side in a radial direction of the first support pillar in a first region and extending to the opposite side of the substrate with respect to the first conductive layer; and a second contact electrically connected to a second conductive layer with a diameter size smaller than a diameter size of a second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer.

Growing community of inventors

Yokkaichi, Japan

Kojiro Shimizu