Matsushita Electric Industrial Co., Ltd.

Matsushita Electrical Co. Ltd.

Koji Zaiki

Tetsuya Tanaka

Shinji Sasaki

Katsuyuki Kaneko

Tadashi Okamoto

Takao Yamamoto

Shinji Furuya

Satoshi Gokita

A processor for controlling execution of instructions stored in a main storage and interruption processing, comprises: interruption processing control device operable to accept an interruption request, analyze an accepted interruption to obtain a cause of the interruption, and generate information indicating a storage position in the main storage of a procedure for processing the cause of the interruption; specific address holding device operable to hold first address information obtained from the information generated by the interruption processing control device; and instruction execution control device operable to decide whether or not the first address information held by the specific address holding device is to be used as information indicating a storage position of an instruction to be executed and control instruction execution according to a decision result.

Processor

The present invention intends to provide an instruction prefetching apparatus capable of reducing a delay caused by branch prediction error by prefetching instruction based on a condition of a conditional branch instruction if the condition is already determined at the prefetching of the branch instruction. In the apparatus, a first decoding unit judges whether or not a processed instruction is a conditional branch instruction or not and whether or not the instruction is a condition generate instruction which determines branch condition. A condition determination signal generating means compares an address of a condition generate instruction with the content of a program counter to judge whether the condition is already determined or not, and according to the judgment, outputs a condition determination signal to a condition determination judging unit. In response to the signal input, the condition determination judging unit outputs prefetch address information for generating address to a prefetch address generating unit, using a condition code.

Instruction prefetching apparatus and instruction prefetching method for

A video-on-demand system divides compressed image data of a video program into image data sections with a predetermined length and stores them in one of a series of storage media in order of reproduction, returning to a first storage medium in the series after reaching a final storage medium in the series, along a story of the video program. The image data sections stored in the storage media are read by time sharing and the original images are reproduced and displayed.

Video-on-demand system uses adjusting positions of slots in a slot table

The present invention relates to an optimizing compiler apparatus for converting a source program into an object program for use by a parallel computer, which optimizes the number of data transmissions between processing elements for a parallel computer made up of a plurality of processing elements, composed of a loop retrieval unit for retrieving the loop processes from a program, a data transmission calculation unit for calculating the data transmission count generated when each of the loop processes is parallelized, a parallelization determination unit for determining the loop to be parallelized as the loop, out of all the loops in a multiple loop, with the lowest data transmission count and a code generation unit for generating parallelized object code for the determined loop. The data transmission calculation unit is made up of a right side variable retrieval unit for retrieving the variables on the right side of an equation in the loop retrieved by the loop retrieval unit, a variable information storage unit for storing information relating to array variables which should be distributed among every processing element for the part of the program which comes before the loop retrieved by the loop retrieval unit and a calculation unit for calculating the data transmission count based on the variable information for the retrieved right side variable.

Device and method for parallelizing compilation optimizing data

The present invention provides an apparatus for detecting possibility to process in parallel a program including a loop where iteration processing is executed comprising a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing information based on the simulation as to a variable whose value is defined in a program statement in relation with information showing a location where in the program the value of the variable is defined, and a judgement unit for judging whether or not parallel processing is possible by referring to the variable storage unit for information of the location; The present invention further provides a program translation apparatus for generating a program applicable to parallel processing based on the detected possibility of executing the program in parallel comprising the simulation unit, the variable storage unit, the judgement unit, and the program generation means for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

Apparatus for detecting possibility of parallel processing and method

The present invention provides an apparatus for detecting whether a program having an iterative loop can be processed in parallel. The apparatus includes including a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing values of variables that are defined by program statements executed during simulation of the iterations, each stored variable being stored with information showing a location in the program where the value of the variable is defined and the simulated iteration number during which the variable is defined, and a judgement unit for judging that parallel processing is possible when, for each simulated iteration, variables appearing undefined in any program statements of that iteration are defined in preceding program statements within that iteration. The present invention further provides a program translation apparatus for generating a program applicable to parallel processing if a possibility of executing the program in parallel is detected. The program translation apparatus includes the simulation unit, the variable storage unit, the judgement unit, and program generation circuitry for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

A compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for parallel execution by a multi-processor computer, without intervention by a programmer. Single loops or nested loops in source program are detected, and where possible are coded for concurrent execution of the outermost loop, with loop interchange in a nested loop, or fission of a loop into a plurality of adjacent loops being performed if necessary to enable concurrentization.

Processor scheduling method for iterative loops

The buffer device array includes plural buffer devices connected to a bus, wherein the buffer devices hold the respective device addresses and device selection signals in the course of a data transfer operation and subsequently the device addresses and device selection signals held in the devices are used for inspecting devices with respect to whether they can be used for the next data transfer operation, thus enabling the data transfer operation and checking of device status for the next data transfer to be performed in a pipeline fashion and significantly increasing the efficiency of the data transfer operation and of the overall bus utilization.

Data buffer device using first-in first-out memory and data buffer array

A memory device comprises an address input, first decoder for decoding an address input applied to the address input means, two-port data storage for storing data, a tag field provided for each of word areas of the data storage means, means for reading data through the first port of the data storage means, data input/output means for writing in and reading out data through the second port of the data storage means, selecting means for selecting data read out through the first port of the data storage means or data externally inputted through the data input/output means, second decoding means for decoding an output data from the selecting means into an address, and control means for controlling reading out of data through the first port of the data storage means, controlling writing in and reading out of data through the second port of the data storage means, and operating in synchronism with an externally supplied clock signal for controlling marking in the tag fields selected sequentially according to address data inputted from the outside through the data input/output means.

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Kadoma, Japan

Koji Zaiki