Mitsubishi Electric Corporation

Koji Tsutsumi

Mitsuhiro Shimozawa

Sho Ikeda

Masaomi Tsuru

Yuki Yanagihara

Wataru Yamamoto

Takaya Maruyama

Eiji Taniguchi

Takanobu Fujiwara

Atsushi Kato

Akihito Hirai

Nobuhiko Ando

Morishige Hieda

Takayuki Nakai

Hiroyuki Mizutani

Ryosuke Takeuchi

Kazuhide Higuchi

Tatsuya Hagiwara

Shinichi Inabe

A first phase shift circuit amplifies, when a first signal, a second signal having a phase difference of 90 degrees from the first signal, a third signal having a phase difference of 180 degrees from the first signal, and a fourth signal having a phase difference of 270 degrees from the first signal are output from a 90-degree distributor that distributes an input signal, each of any three signals from among the first signal to the fourth signal. A second phase shift circuit amplifies each of any two signals of any three signals and one signal that is not amplified by the first phase shift circuit from among the first signal to the fourth signal. One or more phase shift circuits of the first phase shift circuit and the second phase shift circuit each include a compensation circuit that compensates for a phase error of the synthesized signal.

Phase shifter and antenna device

A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase shift amount and with a frequency being twice the frequency of the input signal; and a 90-degree combiner for applying a phase difference of 90 degrees between the first signal and the second signal, and combining the first signal having the phase difference of 90 degrees from the second signal with the second signal.

Phase-variable frequency multiplier and antenna device

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Phase synchronization device

A radar device includes a transmission module, a reception module, and a signal processing unit. The transmission module includes an RF signal source that generates a transmission chirp signal synchronized with a reference signal. The reception module includes an RF signal source that generates a reception chirp signal used as a reception local signal and synchronized with the reference signal. The reception module receives a reflected wave of the transmission chirp signal emitted from the transmission module, and mixes a received reception signal with the reception chirp signal. The signal processing unit detects a target based on a beat signal generated by the mixing by the reception module. The signal processing unit controls at least one of the RF signal sources such that between the transmission chirp signal and the reception chirp signal are output at timings shifted from each other, and corrects a change in a phase difference between the transmission module and the reception module, using a phase of a signal of a direct wave from the transmission module to the reception module.

Radar device, control circuit of radar device, and storage medium of radar device

A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.

Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit

A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.

Variable gain amplifier

A lock detection circuit is configured to include an integrating circuit that integrates a phase difference between a frequency-divided signal of a VCO and a reference signal during a constant period within a transient response period for an output signal from the VCO, and integrates a phase difference between the frequency-divided signal and the reference signal during a constant period within a convergence period for the output signal from the VCO; and a degree-of-convergence calculating circuit that calculates a degree at which the output signal from the VCO has converged, from a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the transient response period and a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the convergence period.

Lock detection circuit and phase-locked loop circuit

A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At &#x394;&#x3a3; modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.

PLL circuit

A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the generated negative feedback signal and the division ratio setting signal to the division ratio control circuit.

Phase-locked loop circuit

A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

A first transistor, a second transistor, a third transistor, and a fourth transistor, their source terminals being grounded, are provided. Further, a first feedback circuit connected between a gate terminal and a drain terminal in the first transistor, and having first impedance, a second feedback circuit connected between a gate terminal and a drain terminal in the second transistor, and having the first impedance, a current source for outputting a current, a first load circuit connected between the drain terminal of the first transistor and a first output terminal of the current source, and having second impedance, and a second load circuit connected between the drain terminal of the second transistor and a second output terminal of the current source, and having the second impedance are provided.

Current amplifier

A lock detector () detects an unlocked state from an output of a phase frequency comparator (). A counter () counts a reference signal, in a case where an unlocked state is detected by the lock detector (). A parameter controlling circuit () acquires the count value of the counter (), and controls switching on and off of a switch () for a D/A converter () that generates a signal to be added to an output of a loop filter (), and the output voltage of the D/A converter () so that the count value of the counter () falls within a set value.

A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

Signal generating circuit

A variable gain amplifier () includes: a signal transmission circuit () including amplifying transistor units (to, andto) connected in parallel between a signal input port (P,N) and a signal output port (P,N); a load circuit () connected between a supply line of power supply voltage (VDD) and an output end of the signal transmission circuit (); a signal short circuit () including a short-circuit transistor unit () connected between the supply line of the power supply voltage (VDD) and an input end of the signal transmission circuit (), a constant-current source circuit (), and a transistor control circuit (). The transistor control circuit () selects transistor units to be turned on, from among the amplifying transistor units (to, andto) and the short-circuit transistor unit (), and supplies control voltages for turning on the selected transistor units.

There are provided: a table memory to store a relation between a control code and gains of variable gain amplifiers; a gain controller to apply the gains to the variable gain amplifiers; an amplitude phase detector to detect amplitude and a phase from an output signal of the vector sum phase shifter; an amplitude phase recorder to record, when the gains are applied by the gain controller, a combination of a control code corresponding to said gains and the amplitude and the phase detected by the detector; and a table calibrator to find a phase shift characteristic of a vector summed part from records of the amplitude phase recorder and calibrate the relation between a control code and gains recorded in the table memory by using the phase shift characteristic.

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Tokyo, Japan

Koji Tsutsumi