Seiko Epson Corporation

Kabushiki Kaisha Suwa Seikosha

Koji Takeda

Masao Akahane

Chitoshi Takayama

Fumiaki Mukaiyama

Yasuhiko Kudo

An apparatus and method for controlling the bus cycle running time of a data processing apparatus. The apparatus includes a CPU and at least one device such as a memory device, input/output device and the like which receives data from the C. A clock signal supplied to the CPU is varied based on the bus cycle or address within the device which is identified by the CPU for processing of the data. Alternatively, the frequency of the clock signal is varied based on ambient temperature and line voltage conditions. Accordingly, processing speed of the CPU can be varied to accommodate high speed memory devices and slower speed input/output devices.

Apparatus and method for controlling the running of a data processing

A system for improving access time to video display data uses a shadow memory having fewer storage locations than a display memory. The shadow memory and the display memory share a set of addresses such that data written to the display memory, at an address shared by the shadow memory, is identically written to the shadow memory. Read requests directed to the display memory result in: (a) data returned from the shadow memory when access to a shared address is requested, and (b) data returned from the display memory when access to a non-shared address is requested.

System for improving access time to video display data using shadow

A computer system having a microprocessor that provides bus control signals indicative of bus transaction types such as memory read, memory write, I/O read, and I/O write, generates a variable frequency clock for use by the microprocessor. The computer system also includes a clock generator and a control circuit. The control circuit instructs the clock generator to provide one of a plurality of clock frequencies based on the type of bus transaction specified by the CPU's bus control signals. Typically, I/O transactions cause the control circuit to instruct the clock generator to provide a low frequency clock. In an alternative embodiment, address signals may be used in conjunction with the bus control signals to define which one of a plurality of clock frequencies shall be selected.

CPU clock generator having a low frequency output during I/O operations

A memory apparatus has a W(1+J/N) (words).times.D (bits) configuration employing (N+J) semiconductor memory units having (N+J) W (words).times.B (bits) semiconductor memory elements wherein N=D/B=2.sup.d-b and J is a positive integer wherein J&lt;N; W=2.sup.w and w is a positive integer; and B=2.sup.b where b is zero or a positive integer satisfying b&lt;d. For example, five 256K.times.4 1M DRAMs are employed so that four out of five DRAMs always correspond to access from a microprocessor. Furthermore, a 640-Kbyte memory address space is equally divided into five 128-Kbyte memory address areas and the correspondence between the 128-Kbyte memory address areas and four out of the five DRAMs is regularly determined in turn, thereby constituting a 640-Kbyte memory apparatus (320 Kwords.times.16 bits) employing only 1M DRAMs. More particularly, a memory capacity can be set in relatively small units, i.e., in units of W.multidot.J/N words.times.D bits by employing only semiconductor memory units of a single type.

Memory apparatus having flexibly designed memory capacity

An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2.sup.n where n is a natural number. A control unit produces a control signal based on the count value of the first counter. The second counter has a variable frequency dividing ratio which is based on the control signal. The counting device can be made programmable by substituting a comparator circuit for the control unit. The comparator compares the output of the first counter to an instruction signal from an external source.

Asynchronous counter

A FSK demodulation circuit using counter techniques to distinguish between two transmitted frequencies, provides a delay preceding the change points of the demodulated signal to reduce signal distortion. Presettable counters reduce the number of data bits for processing, and a plurality of counters count an equal plurality of zero-cross intervals to reduce distortion. Registers and multiplexer further reduce circuit complexity.

FSK Demodulation circuit

Storage space in this speech synthesizer is minimized by features including multiplex storage of voiceless phonemes and use of a word designator which selects in parallel information from a word memory and phoneme memory.

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Suwa, Japan

Koji Takeda