Renesas Electronics Corporation

Koji Takayanagi

Masashi Arakawa

Tadashi Fukui

A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.

Semiconductor device

A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.

A semiconductor device includes: a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a logical signal, the level shift circuit including a series coupling circuit coupled to a second power supply, a control circuit coupled to the series coupling circuit for controlling the series coupling circuit based on the logical signal, and a first potential conversion circuit coupled between the series coupling circuit and the control circuit and coupled to a first power supply. The series coupling circuit includes a plurality of first MOS transistors coupled in series between the second power supply and a reference power supply, and a plurality of second MOS transistors coupled in series between the second power supply and the reference power supply in series with the plurality of first MOS transistors.

When a signal of high amplitude is outputted, a drain-to-source voltage exceeding a withstand voltage may be applied. The semiconductor device according to the present invention includes a level shift circuit that outputs a high amplitude signal from the input of a low amplitude logical signal. The level shift circuit includes a series coupling circuit, a first gate control circuit coupled to a first power supply, a second gate control circuit coupled to a second power supply of a potential higher than the potential of the first power supply, and a potential conversion circuit arranged between the first gate control circuit and the series coupling circuit. The potential conversion circuit supplies a first level potential, which is lower than the potential of the first power supply and higher than the potential of the reference power supply, to a gate of an N-channel MOS transistor of the series coupling circuit.

Growing community of inventors

Tokyo, Japan

Koji Takayanagi