Micron Technology Incorporated

Kabushiki Kaisha Toshiba

Unisantis Electronics Singapore Pte. Ltd.

Honda Motor Co., Ltd.

Tokyo Institute of Technology

Sony Corporation

Other

Tokyo Shibaura Denki Kabushiki Kaisha

Koji Sakui

Nozomu Harada

Peter Sean Feeley

Masakazu Kakumu

Junichi Miyamoto

Fujio Masuoka

Takehiro Hasegawa

Tomoharu Tanaka

Toru Tanzawa

Akira Goda

Takashi Mori

Masaki Momodomi

Kazunori Ohuchi

Shigeyoshi Watanabe

Haitao Liu

Krishna Kumar Parat

Shigekazu Yamada

Han Zhao

Tsuneaki Fuse

Riichiro Shirota

Kenichi Imamiya

Seiichi Aritome

Aurelio Giancarlo Mauri

Takayuki Ohba

Yoshihisa Iwata

Jeremy Binfet

Mark A Hawes

Yoshiyuki Tanaka

Koji Hashimoto

Ken Takeuchi

Yuji Takeuchi

Seiichi Mori

Yasuo Itoh

Koji Yamakawa

Kazuhide Abe

Toshiki Seshita

Akihiro Nitayama

Masayuki Ichige

Hiroshi Toyoda

Toshio Yamamura

Toshiharu Watanabe

Motomasa Imai

Tatsuaki Kuji

Michio Nakagawa

Shinji Saito

Fumitaka Arai

Kazuhiro Suzuki

Mark Alan Helm

Koichi Kawai

Nobuo Hayasaka

Akira Umezawa

Fumio Horiguchi

Hiroshi Nakamura

Tsutomu Nakajima

Toshihiko Himeno

Ryan G Fisher

Mitsuo Harata

Hideki Sumihara

Kenji Kozakai

Yasushi Matsuyama

Ryo Mitani

Katsuya Okumura

Mitsuhiro Noguchi

Tetsuo Endoh

Kikuko Sugimae

Yukihito Oowaki

Yoshio Iizuka

Yutaka Okamoto

Atsuhiro Sato

Chiaki Takubo

Mie Matsuo

Keiichi Sasaki

Kaoru Tokushige

Yohji Watanabe

Jun Sumino

Hideko Oodaira

Mitsugi Ogura

Kenji Numata

Tsunetoshi Arikado

Yoshihisa Sugiura

Takeshi Ishimoto

Daisuke Yoshioka

Hiroshi Ikeda

Hisakazu Iizuka

Kei Takano

Kazuhisa Kanazawa

Hidemi Ishiuchi

Masako Ohta

Satomi Nakano

Aurielo Giancarlo Mauri

Kazuto Kamimura

Provided is a semiconductor device including a memory cell and a MOS transistor. The memory cell includes a first gate insulating layer and a first gate conductor layer surrounding a first pillar-shaped p layer erected on a first p layer substrate, and a second gate insulating layer, a second gate conductor layer, and Nlayers surrounding a second pillar-shaped p layer connected to the first pillar-shaped p layer. The MOS transistor includes a third pillar-shaped p layer erected on a second p layer substrate connected to the first p layer substrate, and a third gate insulating layer, a third gate conductor layer, and Nlayers surrounding a fourth pillar-shaped p layer placed on and in contact with the third pillar-shaped p layer. In a vertical direction, the second pillar-shaped p layer has a length shorter than a length of the fourth pillar-shaped p layer.

Semiconductor device including memory element

By controlling voltages applied to plate lines, word lines, source lines, and bit lines, a memory device that uses semiconductor elements performs a data retention operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a memory erase operation of removing positive hole groups from inside the semiconductor base material. The memory device also performs a data erase operation during the memory erase operation to remove positive hole groups from inside the semiconductor base material of all the memory cells in a block made up of the memory cells, which are arrayed in a matrix.

Semiconductor element memory cell and semiconductor element memory device

A memory device is formed with at least one memory array, the memory array being formed with a plurality of pages and a plurality of bit lines, each page being formed with a plurality of memory cells arranged in a row direction on a substrate in a plan view, the plurality of memory cells being connected to the bit lines disposed in a column direction. Each of the memory cells included in each of the pages includes a semiconductor base material, a first impurity region and a second impurity region positioned in respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer. In the memory cell, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first and second gate conductor layers is connected to a word line, and the other is connected to a plate line. A page erase operation, a page write operation, and a page read operation are performed by controlling a voltage applied to each of the source line, the bit line, the word line, and the plate line. At least one of the bit lines and one of the pages are selected in the page erase operation, the page write operation, and the page read operation, and an erase operation on the memory cell connected to both the bit line and the page thus selected, a write operation of storage data of the sense amplifier circuit to the memory cell, or a read operation from the memory cell to the sense amplifier circuit is executed.

Memory device including semiconductor element

Si bodiestoto, andtoare disposed parallel to a substrateand are adjacent to each other in a horizontal direction at regular intervals. A HfOlayersurrounds the Si bodiesto. TiN layerstosurround the HfOlayer, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodiestoare formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layerstoare connected to the TiN layerstoand extend up to above an insulating layerthrough contact holestoextending in a vertical direction from the terminating ends of the TiN layersto. The metal wiring layerstoare connected to word lines WLto WL

Semiconductor-element-including memory device

A semiconductor element memory device is configured to perform a data hold operation of controlling voltages to be applied to a plate line, a word line, a source line, and a bit line to hold, in a semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate line, the word line, the source line, and the bit line to discharge the positive hole group from the semiconductor base. The semiconductor element memory device includes a plurality of memory cells arranged in a matrix within a block, and constantly manages, using a controller circuit and a logical/physical conversion table, which physical block address of a dynamic flash memory corresponds to data stored in a logical block address.

Semiconductor element memory device

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.

Memory device using semiconductor element

A data retention operation of holding positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base body is performed by controlling voltages applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines; and a data erase operation is performed by removing positive hole groups from inside the semiconductor base body by controlling the voltages applied to plate lines, word lines, source line, odd-numbered bit lines, and even-numbered bit lines and lowering a voltage of The semiconductor base body by means of capacitive coupling between the plate lines and word lines. A block is made up of memory cells arrayed in a matrix, and storage data is read from the memory cells in the block alternately to the odd-numbered bit lines and even-numbered bit line.

A memory device includes a page constituted by multiple memory cells arranged in a row form on a substrate, and performs a page write operation of controlling voltages to be applied to first and second gate conductor layers and first and second impurity layers of each memory cell included in the page to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; During a page read operation, page data of a memory cell group selected with the word line is read to the sense amplifier circuit, and a refresh operation is performed at least once before the page read operation to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer.

Memory device using dynamic flash memory cells

A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.

A dynamic flash memory includes a p layer as a semiconductor base material, first and second nlayers on opposite sides thereof, first and second gate insulating layers in contact with each other and partially covering the p layer, and first and second gate conductor layers electrically isolated from each other and respectively provided on the first and second gate insulating layers. The first and second nlayers and first and second gate conductor layers are respectively connected to source, bit, word, and plate lines. During writing, 1.0 V, 1.5 V, and 1.2 V are sequentially applied to the bit, plate, and word lines, respectively. During erasing, 2 V is applied to the plate line, and then, a voltage applied to each terminal is always set 0 V or greater (e.g., 0.6 V for the bit line). Further, during reading, voltages are sequentially applied to the bit, plate, and word lines.

Memory device with semiconductor elements

A memory device includes pages each constituted by a plurality of memory cells arranged in columns on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each page are controlled to perform a page write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the semiconductor body and further lowering a voltage of the semiconductor body with capacitive coupling with the first gate conductor layer and with the second gate conductor layer, and in the page erase operation, at least two or more pages are simultaneously selected from among the pages and the page erase operation is performed.

There is provided a columnar semiconductor memory device in which a data retention operation is performed in which voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the first gate conductor layer and capacitive coupling with the second gate conductor layer.

A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Semiconductor memory device

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data '1'. The refresh operation is performed continuously to an N-th page group.

Growing community of inventors

Setagaya-ku, Japan

Koji Sakui