Hitachi, Ltd.

Koji Saito

Takashi Hotta

Shigeya Tanaka

Kotaro Shimamura

Hideo Sawamoto

Toshihiko Kurihara

Akiyoshi Osumi

Masatoshi Kanamaru

Ryo Miyake

Takao Terayama

Masao Fukunaga

Hideo Enoki

Tamio Ishihara

Sadao Mori

Katsutoshi Yamada

Shoji Yoshida

Kenji Jin

A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Data processor having cache memory

A water quality meter is composed of a plurality of water quality monitoring meters including analyzing units for analyzing water samples introduced from a water distribution pipe, each analyzing unit analyzing the water samples and a measuring cell, and a liquid introducing unit integrated with the analyzing units, which is composed of a single member in which a plurality of fluid flow paths for feeding various types of liquid including the water sample into the analyzing unit are formed. Furthermore, the cells and the plurality of three-dimensional fluid flow paths formed in the single member are fabricated by a micro-fabrication technique using photo-curing resin.

Water quality meter and water quality monitoring system

A water quality meter is composed of a plurality of analyzing units for analyzing water samples introduced from a water distribution pipe, each analyzing unit including a reagent mixing cell and a measuring cell, and a liquid introducing unit integrated with the analyzing units, which is composed of a single member in which a plurality of fluid flows paths for feeding various types of liquid including the water sample into the analyzing unit are formed. Furthermore, the cells and the plurality of three-dimensional fluid flow paths formed in the single member are fabricated by a micro-fabrication technique using photo-curing resin. In one embodiment, a photometer is situated in the flow path in at least one analyzing unit for measuring absorbency of the liquid. In another embodiment, a pair of electrodes, for measuring electric conductivity or pH, is disposed in a measurement flow path in at least one of the analyzing units.

A water quality meter is composed of a plurality of analyzing units for analyzing water samples introduced from a water distribution pipe, each analyzing unit including a reagent mixing cell and a measuring cell, and a liquid introducing unit integrated with the analyzing units, which is composed of a single member in which a plurality of fluid flow paths for feeding various types of liquid including the water sample into the analyzing unit are formed. Furthermore, the cells and the plurality of three-dimensional fluid flow paths formed in the single member are fabricated by a micro-fabrication technique using photo-curing resin.

Water quality meter and water monitoring system

Data processor with variable types of cache memories and a controller for selecting a cache memory to be access

Data processor with variable types of cache memories

A microprocessor has N processing units, a detector for detecting a branch instruction (k-th instruction) which comes first in the instruction sequence of N instructions, function logic for effecting control such that the first to the k-th instructions are executed with the (N-k+1)-th through the N-th processing units. However, when parallel processing is possible, the function logic operates such that the first through the N-th instructions are executed in sequential order by the first through the N-th processing units. On the other hand, wherein a branch instruction (k-th instruction) is included in the N sequential instructions, the function logic operates such that the first through the k-th instructions are parallelly executed by the (N-p+1)-th through the N-th processing units.

Microprocessor

Growing community of inventors

Hadano, Japan

Koji Saito