Renesas Technology Corp.

Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Other

United Microelectronics Corp.

Attopsemi Technology Co., Ltd

Renesas Electronics Coporation

Renesas Electronics Corportion

Renesas Electroncis Corporation

Koji Nii

Makoto Yabuuchi

Yasumasa Tsukamoto

Koichiro Ishibashi

Hiroshi Makino

Hirofumi Shinohara

Shigeki Obayashi

Masanori Isoda

Masanao Yamaoka

Shigeki Ohbayashi

Yasuhisa Shimazaki

Noriaki Maeda

Yoshihiro Shinozaki

Yuichiro Ishii

Yoshikazu Saito

Hidehiro Fujiwara

Takashi Ipposhi

Shigeto Maegawa

Yuuichi Hirano

Yasunobu Nakase

Motoshige Igarashi

Shoji Okuda

Kengo Masuda

Hideshi Maeno

Shinji Tanaka

Atsushi Miyanishi

Nobuhiro Tsuda

Yoshinori Okada

Kazutami Arimoto

Shine Chien Chung

Chun-Hsien Huang

Hideaki Abe

Tetsuya Watanabe

Yu-Tse Kuo

Takeshi Fujino

Makoto Hatakenaka

Kazunari Inoue

Ching-Cheng Lung

Yoshiki Tsujihashi

Yohei Sawada

Koji Shibutani

Hisashi Matsumoto

Atsuo Mangyo

Tien-Yu Lu

Tomoaki Yoshizawa

Susumu Imaoka

Shou-Sian Chen

Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.

Programmable resistive memory formed by bit slices from a standard cell library

A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

Semiconductor device

Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

Semiconductor memory device

To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.

A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.

A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P), and an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P). The inverters (II) are subjected to cross section. The NMOS transistor (N) is formed within a P well region (PW), and the NMOS transistor (N) is formed within a P well region (PW). The P well regions (PWPW) are oppositely disposed with an N well region (NW) interposed therebetween.

Semiconductor memory

In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Static random access memory device with halo regions having different impurity concentrations

A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P), and an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P). The inverters (II) are subjected to cross section. The NMOS transistor (N) is formed within a P well region (PW), and the NMOS transistor (N) is formed within a P well region (PW). The P well regions (PW, PW) are oppositely disposed with an N well region (NW) interposed therebetween.

A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.

Dual port static random access memory (DPSRAM) cell

In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Semiconductor memory device for stably reading and writing data

Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage

A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Semiconductor device having capability of generating chip identification information

Growing community of inventors

Tokyo, Japan

Koji Nii