Fujitsu Corporation

Koji Nakamuta

Yoshito Koyama

Hisao Nakashima

Nobukazu Koizumi

Noriyasu Nakayama

Takeshi Hoshida

Takahito Tanimura

Kazuhiko Hatae

Kosuke Komaki

Manabu Yamazaki

Ken Atsumi

Masashi Sato

Minoru Hirahara

Hideyuki Matsuura

Tomoki Katou

Yoshifumi Nakajima

Minoru Sakai

A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.

Optical communication receiving device and frequency offset compensation method

A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.

Digital coherent receiving apparatus

An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.

Adaptive equalizer, optical receiver, and tap coefficient correcting method

A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

PLL circuit, method of controlling PLL circuit, and digital circuit

An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.

Analog-digital converting apparatus and clock signal output apparatus

A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.

Digital PLL circuit and clock generating method

A thermostatic-chamber temperature control device includes: a heating element for heating a thermostatic chamber; a bridge circuit having a temperature sensitive element whose resistance value varies in accordance with the temperature of the heating element; a detection circuit for detecting an unbalanced voltage of the bridge circuit; a PWM signal generating circuit for generating a PWM signal corresponding to the unbalanced voltage detected by the detection circuit; and a switching element that has a current output terminal connected to the heating element and a current input terminal connected to a power supply circuit and is driven on the basis of the PWM signal generated by the PWM signal generating circuit.

Temperature control device

A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.

Digital PLL circuit

To a frequency divider having a reset function, a second clock of a frequency N&#xd7;Y times higher than that of a first clock is inputted. Upon receipt of a signal indicating that the stop of the input clock is detected by a start/stop detection circuit, the frequency divider having a reset function resets the dividing of a frequency. Then, upon receipt of a signal indicating that the resumption of the input clock is detected by the start/stop detection circuit, the frequency divider generates and inputs a third clock to a phase comparator by starting the dividing of a frequency.

PLL circuit

Each clock supply unit comprises an inter-unit synchronization portion which operates when the clock supply unit is acting as a standby unit, using a clock signal from a DPLL of a unit which is active as reference, to apply a predetermined phase difference to the output clock signal of the DPLL of the unit to cause synchronization with the output clock signal of the DPLL of the active unit.

Clock supply device

The invention relates to a frequency synthesizer. An object of the invention is to provide a frequency synthesizer whose high stable performance is realized at an inexpensive cost. The frequency synthesizer includes a frequency synthesizing section generating an output signal by performing indirect frequency synthesis at a period which is equal to a product of a period of the reference signal and a first integer, and a clock generating section generating the clock signal by performing frequency synthesis for the output signal and for maintaining a frequency of the clock signal at a value which is equal to a difference between or a sum of a first frequency which is equal to a product of the frequency of the reference signal and a second integer and a second frequency indicating a number of times the phase difference is compressed.

Frequency synthesizer

The invention relates to a digital synchronization network, and provides a DPLL circuit having a holdover function that generates a high-precision reference clock with a temperature correction to perform a free-running frequency control at a holdover time. In a holdover mode of the DPLL circuit using a DDS, the DPLL circuit having a holdover function adds a correction value calculated from a temperature characteristic of a slave oscillator to a fixed DDS control value during a detection of a holdover, thereby changing the DDS control value according to the temperature characteristic.

DPLL circuit having holdover function

In an atomic oscillator, a high-frequency converting circuit converts the output of a standard oscillator into a high frequency signal such that the frequency of the high frequency signal multiplied by a low natural number equals an atomic resonant frequency signal. The high frequency signal is then multiplied by a low natural number in an active, low-natural-number multiplier circuit to convert the output frequency of the standard oscillator into a resonant frequency to be input to the atomic oscillator. The result is that, without using a passive, high-natural-number multiplier circuit, such as a varactor diode, which is expensive, it is possible to convert the output frequency of the standard oscillator into a resonant frequency signal of a rubidium atom, thus downsizing the circuits of the atomic oscillator and reducing the term and cost of manufacture.

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Kawasaki, Japan

Koji Nakamuta