Seiko Epson Corporation

Koji Miyashita

Takashi Aoyama

Kiminori Nakajima

Koji Ushiyama

Takashi Kumagai

Yasunobu Tokuda

Masaya Uehara

Tadatoshi Nakajima

A circuit for a physical quantity detection device includes a drive unit that generates a drive signal that causes an vibrator to vibrate, a detection unit that detects a detection signal outputted from the vibrator based on the drive signal, a passive filter which has a filter characteristic in which a cutoff frequency is lower than a detuning frequency and a cutoff frequency band contains a frequency band higher than the cutoff frequency and to which a signal from the detection unit is inputted, and an amplification unit that amplifies a signal from the passive filter.

Circuit for physical quantity detection device, physical quantity detection device, electronic apparatus, and moving object

A semiconductor device having a plurality of memory cells for storing data, an address input circuit having an address signal generation section for independently generating an address signal using a clock signal in a test mode, and a delay circuit for delaying an input time of the address signal from the address input circuit to a subsequent circuit for a predetermined time period which is equal to or longer than the time necessary for the generation of the address signal.

Semiconductor device, method of testing the same and electronic instrument

A semiconductor memory device has a first precharge transistor connecting a potential supply line to one end of a bit line when the bit line is precharged and a second precharge transistor connecting the potential supply line to the other end of the bit line when the bit line is precharged. To a gate of the first precharge transistor is inputted a first precharge signal, and to a gate of the second precharge transistor is inputted a second precharge signal generated based on a chip-select signal and the first precharge signal. The second precharge transistor is brought into a cut-off state during a standby state in which a memory cell corresponding to the second precharge transistor does not read nor write data but holds date.

Semiconductor memory device and electronic instrument using the same

A highly integrated semiconductor memory device capable of operating at high speed having a plurality of main word lines which extend along a first direction across memory blocks, and sub word lines disposed in each of the memory blocks and subordinate to each of the main word lines. Sub row decoders are provided corresponding to the memory blocks. Each of the sub row decoders has a plurality of sub word select signal lines extending along a second direction and selects one of the sub word lines. First and second signal supply sections, which supply sub word select signals to the sub word select signal lines disposed in the sub row decoders, are provided on either end in the first direction. A block select signal line extending in the sub row decoder along the second direction is connected with the second signal supply section. The second signal supply section generates the sub word select signal based on the potential of the block select signal line.

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Matsumoto, Japan

Koji Miyashita