Kabushiki Kaisha Toshiba

Mitsubishi Hitachi Power Systems, Ltd.

Koji Miyamoto

Kenji Yoshida

Hisashi Kaneko

Takeshi Fujimaki

Hiroshi Nakazawa

Shinya Imano

Takeshi Matsuo

Takeshi Izumi

Yuichi Nakashima

Norihisa Matake

Takeshi Matsunaga

Hideyuki Arikawa

Akira Mebata

Masahiro Mihara

Masaki Yasunaga

Tomonori Souda

This method is a method for manufacturing a gas turbine blade, including: The step of partially coating an inner surface of the cooling pass with Al further including:

Method for manufacturing gas turbine blade, and gas turbine blade

Provided is a fuel cell capable of reducing the size thereof by reducing the installation space. The fuel cell includs a plurality of cell tubes, a lower tube plate fixing one end portion of the plurality of cell tubes, a gas flow path portion communicatively connected to an electric power generating chamber through the lower tube plate, a fuel discharge header and an air supply passage provided in the gas flow path portion, in which the fuel discharge header is communicatively connected to an interior of the cell tubes on one surface side and is adjacent to the air supply passage on the other surface and a side surface with a metal member interposed therebetween.

Fuel cell module

Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering &#xb1;40&#xb0; C. of a temperature at which a stress migration is most accelerated.

Method of accelerating test of semiconductor device

A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

Semiconductor device having capacitor formed in multilayer wiring structure

There is provided a method of manufacturing a semiconductor device having a number of wiring layers, comprising forming an underlayer, the underlayer including a substrate, at least one underlayer wiring layer provided on the substrate, and a first attachment surface, forming at least one upper structure, the upper structure including at least one upper wiring layer and a second attachment surface, and positioning the upper structure and the underlayer and attaching the first and second attachment surfaces to each other.

Semiconductor device having multilayer wiring and manufacturing method therefor

One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Semiconductor integrated circuit device having multilevel interconnection

An insulating film has steps on its surface according to the steps on the substrate. The surface of the insulating film is planarized by CMP. The insulating film has thick portions and thin portions. In the thick and thin portions of the insulating film, first and second contact holes are made. The diameter of shallow second contact holes made in the thin portions of the insulating film is set smaller than that of deep first contact holes made in the thick portions of the insulating film. The first and second contact holes are filled with tungsten simultaneously by CVD techniques to form first and second contacts. The surfaces of the first and second contacts coincide with the surface of the insulating film.

Growing community of inventors

Yokohama, Japan

Koji Miyamoto