Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Koji Matsuki

Yasoji Suzuki

Hideharu Egawa

A clock generator contained in an integrated circuit has an input terminal, a first output terminal, and a second output terminal. When the input terminal of this clock generator receives a basic clock signal supplied by an external integrated circuit, the first output terminal outputs a first clock signal in response to the basic clock signal, and the second output terminal outputs a second clock signal which is an inverted clock signal of the first clock signal in response to the basic clock signal. When the input terminal receives a constant level signal supplied by the external integrated circuit, the first output terminal and the second output terminal output respectively the same constant level signal to thus provide reduced power consumption.

Clock generator circuit providing reduced current consumption

A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Complementary semiconductor device

A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Method for preparing complementary semiconductor device

A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. The N- and P-channel type silicon gate field effect transistors are formed in the P- and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Growing community of inventors

Yokohama, Japan

Koji Matsuki