Hitachi, Ltd.

Other

Hitachi Process Computer Engineering, Inc.

Koji Masui

Masayuki Tanji

Hiroaki Fukumaru

Nobuyasu Kanekawa

Yoshiki Kobayashi

Tomoaki Nakamura

Shigenori Kaneko

Takeshi Miyao

Manabu Araoka

Kazuhiko Ishii

Saburou Iijima

Masahiro Matsuda

Katsunori Tagiri

Shigeru Udono

Shinichiro Kanekawa

Yoshihiro Miyazaki

Hisao Ogawa

Kunio Suzuki

Syoji Yamaguchi

Kunihiko Onuma

In a boiling water reactor controlling each control rod hydraulically by driving a solenoid valve, the control system comprises an operation control meanshaving a duplicated data processing unit for generating sequence patterns based on the timing of the driving sequence based on the control information provided manually, a transmission control meansfor creating a command word corresponding to each control rod being controlled based on said sequence pattern, and mutually communicating each command word between duplicated data processing units and computing the AND logic of said data within a predetermined time difference, and when the computed result coincide, transmitting the selected command word serially; a transmission unitfor receiving said command word and performing protocol conversion thereto, and transmitting the same to a plurality of transmission branch units positioned downstream as the control command; and a solenoid valve drive circuitfor driving the control rod drive unit corresponding to each rod branched from said transmission branch units.

Reactor manual control system

In a boiling water reactor controlling each control rod hydraulically by driving a solenoid valve, the control system comprises an operation control means having a duplicated data processing unit for generating sequence patterns based on the timing of the driving sequence based on the control information provided manually, a transmission control means for creating a command word corresponding to each control rod being controlled based on said sequence pattern, and mutually communicating each command word between duplicated data processing units and computing the AND logic of said data within a predetermined time difference, and when the computed result coincide, transmitting the selected command word serially; a transmission unit for receiving said command word and performing protocol conversion thereto, and transmitting the same to a plurality of transmission branch units positioned downstream as the control command; and a solenoid valve drive circuit for driving the control rod drive unit corresponding to each rod branched from said transmission branch units.

A computer system has a plurality of processing units (,-,-,-n) connected via one or more system buses (,-,-,). Each processing unit (,-,-,-n) has three or more processors (,-,-,-,) on a common support board (PL) and controlled by a common clock unit (,). The three processors (,-,-,-,) perform the same operation and a fault in a processor (,-,-,-,) is detected by comparison of the operations of the three processors (,-,-,-,). If one processor (,-,-,-,) fails, the operation can continue in the other two processors (,-,-,-,) of the processing unit (,-,-,-n), at least temporarily, before replacement of the entire processing unit (,-,-,-n). Furthermore, the processing unit (,-,-,-n) may have a plurality of clocks (A,B) within the clock unit (,), with a switching arrangement so that the processors (,-,-,-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (,) may be connected in common to the processors (,-,-,-,), so that failure of one cache memory (,) permits the processing unit (,-,-,-n) to continue to operate using the other cache memory (,). Coherence of the contents of the cache memories (,) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (,-,-,-,) of a processor (,-,-,-,) which differs from that in the external cache memory (,). Coherence of protocols may also ensure that data in caches (,) of the different processor units (,-,-,-n) are always correct.

Processing unit for a computer and a computer system incorporating such a processing unit

A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

Processing unit for a computer and a computer system incorporating such

A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

Method and apparatus for controlling dual bus system

An interruption signal from a common input/output device is coupled to all processors through a common bus, and each processor issues to the common bus its own interruption receipt acceptance or negation state and the respective processors watch and decide individually interruption receipt acceptance or negation states on the common bus of the individual processors. Only one of processors which are ready to accept the receipt of interruption is allowed to accept the receipt of an interruption signal from the common input/output device in accordance with a predetermined priority.

Method and apparatus for interruption processing in multi-processor

A magnetic bubble file system having a magnetic bubble memory includes magnetic bubble memory devices as memory media for constructing a plurality of pages of information store areas read and written by page. The store area of a selected one of the plurality of pages of the magnetic bubble memory devices is allotted to a write protection information store page for the magnetic bubble memory. The write protection information store page stores write protection information of each page of data store pages of the magnetic bubble memory. The magnetic bubble file system determines whether data can be written in to the data store page, in accordance with the write protection information stored in the write protection information store page.

Magnetic bubble file system

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Hitachi, Japan

Koji Masui