Sharp Kabushiki Kaisha Corporation

Koji Komatsu

Daisuke Azuma

Shinichi Yoshida

Souichi Miyata

Yasuo Suminaga

Yasuhiro Hotta

Mikiro Okada

Tomoyuki Kawai

Takeshi Nojima

Koji Imura

Masaaki Tatsukawa

Toshihiko Yoshinari

A sense-amplifier circuit for a multivalued information storing memory is featured by a reduced current consumption realized without any elongation of delay time, which circuit comprises plural current-mirror sub-sense-amplifiers corresponding to plural reference potentials VREF, wherein those having higher reference potentials among the sub-sense-amplifiers are provided each with a current-limiting switching element QNX.

Sense amplifier circuit

A clock-synchronized memory includes a plurality of memory cells and a plurality of mode registers in which respectively different operation modes are set, the clock-synchronized memory outputting data stored in the plurality of memory cells in one of the respectively different operation modes and in synchronization with a clock signal. The clock-synchronized memory further includes: a detection circuit for detecting a power potential applied to the clock-synchronized memory; and a mode register selection circuit for selecting one of the respectively different operation modes, the selection being made in accordance with an output signal from the detection circuit representing the power potential.

Clock-synchronized memory

A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, a plurality of decoders for selectively activating the plurality of word lines in accordance with an address, and a plurality of banks arranged in a predetermined direction. Each of the plurality of banks is connected to at least one of the plurality of word lines. At least two of the plurality of word lines are connected to one common decoder of the plurality of decoders. Each of at least two of the banks is connected to the at least two word lines of the plurality of word lines. The at least two banks are not adjacent.

Semiconductor memory device with hierarchical bit line architecture

A sense-amplifier circuit comprising a plurality of sub-sense-amplifiers corresponding to respective reference potentials can operate fast when used for a multivalued information memory. The sense amplifier circuit is composed of sub-sense-amplifiers having different polarities according to corresponding reference potentials: a sub-sense-amplifier SN3 having the highest reference potential is of N (polarity) type and a sub-sense-amplifier SP1 having the lowest reference potential is of P (polarity) type. All sub-sense-amplifiers can operate according to improved characteristics assuring a reduced access time.

A semiconductor memory device includes a plurality of main bit lines; a first bank including a plurality of memory cells, a plurality of word lines, and a plurality of sub bit lines; a second bank including a plurality of memory cells, a plurality of word lines, and a plurality of sub bit lines which are independent from the plurality of sub bit lines included in the first bank; a first auxiliary conduction region coupled to one of the plurality of main bit lines; a first switch for electrically connecting the first auxiliary conduction region to a second auxiliary conduction region: and a second switch for electrically connecting one of the plurality of sub bit lines included in the first bank to the second auxiliary conduction region.

Semiconductor memory device

The semiconductor memory device of this invention includes a plurality of blocks and an external bit line extending through the plurality of blocks in a column direction, wherein each of the plurality of blocks includes a plurality of bank regions each including a plurality of memory cells arranged in a matrix, the plurality of bank regions are arranged in the column direction, each of the plurality of blocks has a main bit line, the main bit line of each of the plurality of blocks extends through the plurality of bank regions in the column direction in parallel with the external bit line, to be shared by the plurality of bank regions, and the semiconductor memory device further includes a block selector for receiving a signal from outside for selecting one of the plurality of blocks and activating the main bit line corresponding to the selected block with the external bit line.

A semiconductor memory is arranged so that a first memory cell array is provided on one side of a set of a row decoder and word line driving circuits, while a second memory cell array is provided on an opposite side thereof. In the semiconductor memory thus arranged, the first memory cell array has less memory cells so that the first memory cell array has shorter word lines, so that more speedy access to a top data is achieved. By doing so, the access to the top address is made speedy in the high access mode such as the page mode or the serial access mode, with no increase in chip areas in the semiconductor memory and no increase in power consumption. Furthermore, in a semiconductor memory which stores first data requiring a comparatively higher read-out speed (for example, program data) and second data requiring a read-out speed lower than that of the first data, the first data is stored in the memory cell array having the shorter word lines, while the second data is stored in the memory cell array having the longer word lines. By doing so, read-out speeds in accordance with the types of stored data can be obtained, without wasteful power consumption in the word line driving circuits.

Semiconductor memory device capable of page mode or serial access mode

This is provided a dual-surface mounting type semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power. In the dual-surface mounting type semiconductor integrated circuit device, a specified circuit for implementing a function common to integrated circuit chips and mounted on both surfaces of a chip mounting section of a lead frame is provided only for the integrated circuit chip of one surface, and an output signal of the specified circuit provided only for the integrated circuit chip of this one surface is transmitted to the integrated circuit chip of the other surface via bonding wires and an internal lead.

Semiconductor integrated circuit device capable of achieving reductions

A semiconductor memory device includes a plurality of main bit lines; a first bank having a plurality of memory cells, a plurality of word lines and a plurality of sub-bit lines; a second bank having a plurality of memory cells, a plurality of word lines and a plurality of sub-bit lines; an auxiliary conductive region connected to one of the plurality of main bit lines, the auxiliary conductive region being shared by the first bank and the second bank; a first bank selection transistor for selectively connecting one of the plurality of sub-bit lines of the first bank to the auxiliary conductive region; a second bank selection transistor for selectively connecting one of the plurality of sub-bit lines of the second bank to the auxiliary conductive region; and a first bank selection line shared by the first bank selection transistor and the second bank selection transistor.

Word lines are driven by respective word line driving circuits in a row selector. Bank selection line driving circuits for driving respective bank selection lines of memory cell arrays are arranged on one side of the first memory cell array and between the adjacent memory cell arrays. The bank selection line driving circuits corresponding to the respective memory cell arrays are connected in series from a row selector side. The bank selection line driving circuits drive the bank selection lines of the corresponding memory cell arrays respectively.

Semiconductor storage device having a hierarchical bit line structure

The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.

Semiconductor memory using select transistors coupled to sub-bitlines

In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

Semiconductor storage device

So-called template matching processing is function-distributed into a pre-detecting portion and a template matching portion, processing in the respective portions being achieved by a hardware circuit. In the pre-detecting portion, the relationship between data which simultaneously exist in the determined comparing sections on data transmission paths, and matching processing is performed in advance with respect to data to be matched. The template matching portion includes an addressing type general-purpose memory and performs main processing of template matching based on the result of the comparison and determination in the pre-detecting portion.

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Nara, Japan

Koji Komatsu