Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Koji Kohara

Takehiko Hojo

A flip-flop circuit includes first and second latches. The first latch comprises a first inverting logic element and a second inverting logic element. The first inverting logic element has a first logic threshold voltage. The second inverting logic element is connected in antiparallel to the first inverting logic element and has a second logic threshold voltage. The first and second logic threshold voltages are set with respect to one half of a power supply voltage. The second latch comprises a third inverting logic element and a fourth inverting logic element. The third inverting logic element is connected to the first latch and has a third logic threshold voltage. The fourth inverting logic element is connected in antiparallel to the third inverting logic element and has a fourth logic threshold voltage. The third and fourth logic threshold voltages are set with respect to one half of the power supply voltage.

Flip-flop circuit and asynchronous receiving circuit

According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.

Semiconductor device, clock circuit, and control method of semiconductor device

A semiconductor storage device comprises a memory cell, a write word line and a read word line connected to the memory cell, first and second write bit lines connected to the memory cell, first and second read bit lines connected to the memory cell, a precharge circuit, and a sense amplifier circuit. The precharge circuit is configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential. The sense amplifier circuit is configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell and output a signal corresponding to the difference in potential as a read value.

Semiconductor storage device and operation method thereof

According to one embodiment, a semiconductor memory device includes first, second, third and fourth MOS transistors, and first and second precharge circuits. A memory cell includes the first, second, third and fourth MOS transistors. Source and drain of the third MOS transistor are connected to between the source or the drain of the first MOS transistor and a first bit line. Source and drain of the fourth MOS transistor are connected to between the source or the drain of the second MOS transistor and a second bit line. The first precharge circuit supplies a voltage to the first and second bit lines in a precharge period during a read operation or a write operation. The second precharge circuit supplies the voltage to the first and second bit lines while in a data holding state.

Semiconductor memory device including precharge circuit

According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a connection place of the connection path formed in the first memory cell, and stores data different from the data stored in the first memory cell is stored. The third memory cell varies a connection place from the connection place of the connection path formed in the second memory cell, and stores data same as the data stored in the first memory cell is stored.

Semiconductor storage device and ROM generator

A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.

Semiconductor integrated circuit and redundancy method thereof

A semiconductor integrated circuit is disclosed, which includes a plurality of memory circuits in which defective columns are relievable, mounted on one chip, each of the memory circuits having a multi-bit structure, a plurality of comparison circuit which are connected to output sides of the respective memory circuits, and compare multi-bit memory data items output from the associated memory circuits with multi-bit expected data, a logic circuit which consolidates multi-bit comparison results output from the comparison circuits, a replacement analysis circuit which is shared between the memory circuits, performs replacement analysis by processing multi-bit data output from the logic circuit, and generates relief information to relief the memory circuits, and a nonvolatile storage circuit which stores the relief information, and performs relief for the memory circuits by using the relief information.

Semiconductor integrated circuit and relief method and test method of the same

There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set, and a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.

Semiconductor integrated circuit device

The present invention provides a semiconductor integrated circuit that is provided with an address generation circuit that selectively generates an address of a memory cell substituted by a redundancy memory cell based on a defective memory cell address retained in an address retention circuit, and a control circuit that selectively tests the redundancy memory cell by performing a retest on whether the substitution is successful or not based on the address generated by the address generation circuit.

Semiconductor integrated circuit and testing method therefor

A first fuse element, a second fuse element, a read trim value automatic adjustment circuit, and a fuse data read circuit are provided. The second fuse element determines a data reading condition for the first fuse element. The read trim value automatic adjustment circuit applies a constant voltage across the second fuse element prior to reading data from the first fuse element, then reads data from the second fuse element and, on the basis of the results of the read, outputs a trim value to specify the desired read condition for the first fuse element. The fuse data read circuit applies a constant voltage across the first fuse element and then reads data from it according to the read timing or the read reference voltage set on the basis of the trim value output from the read trim value automatic adjustment circuit.

Growing community of inventors

Yokohama, Japan

Koji Kohara