International Business Machines Corporation

Koji Kitamura

Toshio Sunaga

Hisatada Miyatake

Hideo Asano

Kohki Noda

Hiroshi Umezaki

Sang Hoo Dhong

Toshiaki Kirihata

A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Non-volatile memory device

A magnetic random access memory (MRAM) array is disclosed herein in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, the wordlines including read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, memory elements, respectively, including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through the bitline, and a read wordline driver connected to the memory array adapted to provide a first read signal to a first read wordline of a plurality of read wordlines, wherein a second read signal is provided to activate a second read wordline while the first read wordline remains activated.

MRAM array and access method thereof

A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.

MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SCand SC. The sub-cell SCincludes magneto resistive elements MTJand MTJand a selection transistor Tr, and the sub-cell SCincludes magneto resistive elements MTJand MTJand a selection transistor Tr. The magneto resistive elements MTJand MTJare connected in parallel, and the magneto resistive elements MTJand MTJare also connected in parallel. Further, the sub-cells SCand SCare connected in series between the write/read bit line BLW/R and the ground.

MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC and SC . The sub-cell SC includes magneto resistive elements MTJ and MTJ and a selection transistor Tr , and the sub-cell SC includes magneto resistive elements MTJ and MTJ and a selection transistor Tr . The magneto resistive elements MTJ and MTJ are connected in parallel, and the magneto resistive elements MTJ and MTJ are also connected in parallel. Further, the sub-cells SC and SC are connected in series between the write/read bit line BLW/R and the ground.

A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline and, for generating a stop signal for stopping a data write current supply to the bitline and a write wordline after data is written in an magnetic tunnel junction (MTJ) element . Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline , thereby saving power.

MRAM and access method thereof

The register disclosed herein includes a register block and a data writing block having non-volatile storage elements which store data output therefrom. The disclosed register further includes a data restoring block for reading data from the non-volatile storage elements. In a disclosed embodiment, the non-volatile storage elements are magnetic tunnel junction (MTJ) elements.

Data register and access method thereof

A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

Growing community of inventors

Kusatsu, Japan

Koji Kitamura