Nec Corporation

Japan Science and Technology Agency

Nec Electronics Corporation

Koji Kishimoto

Takashi Yokoyama

Yoshiaki Yamada

Kenichi Koyanagi

Tetsuya Homma

Yasuyoshi Watanabe

Takao Shimizu

Tatsuya Usami

Akira Kubo

Kunihiro Fujii

Ken-Ichi Koyanagi

Novel calcium-independent phospholipases A; genes encoding the same; an antibody against them; an inherent promoter or a regulator gene which comprises a base sequence occurring in intron and inducing site-specific expression in response to an external stimulus; a method of expressing a target protein in response to an external stimulus; and an organism having this gene transferred thereinto. Novel calcium-independent phospholipases Ahaving an amino acid sequence represented by SEQ ID NO: 1, 3 or 5 or an amino acid sequence derived from such an amino acid sequence by the substitution, deletion or addition of one or more amino acids; a gene having a base sequence occurring in an intron and being capable of initiating RNA transcription due to an external stimulus such as a stimulus with kainic acid or an electrical stimulus; a method of regulating expression by using the gene; and an organism having the gene transferred thereinto.

Promoter of novel calcium-independent phospholipase A2

[object Object]

A semiconductor device with satisfactory bonding ability of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for burying wiring space portions. The semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is formed by etching the anti-reflection layer and the metal layer while taking the patterned insulation layer as a mask and leaving the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface thereby.

Semiconductor device having fluorine containing silicon oxide layer as dielectric for wiring pattern having anti-reflective layer and insulating layer thereon

A high density plasma enhanced chemical vapor deposition method for depositing an insulating film such as a silicon oxide film on a silicon substrate includes at least both a first deposition period during which a first power having a first frequency is applied to the silicon substrate and a second deposition period during which a second power having a second frequency which is lower than the first frequency is applied to the silicon substrate to keep an underlying Si/SiO interface free from an interface state, where said underlying Si/SiO interface has already been formed under said insulating film.

High density plasma enhanced chemical vapor deposition method

A method of fabricating a semiconductor device, includes the steps of (a) forming a first insulating film on a semiconductor substrate, (b) forming at least one recess at a surface of the first insulating film, (c) forming a first barrier layer covering a surface of the first insulating film and an inner surface of the recess therewith, (d) forming a copper layer over the first barrier layer such that the recess is entirely filled with the copper layer, (e) polishing the copper layer and the first barrier layer until the first insulating film appears, (f) exposing the copper layer to a plasma including at least one of carbon and hydrogen, (g) forming a second barrier layer on both the copper layer and the first insulating film, and (h) forming a second insulating film on the second barrier layer.

Method of fabricating a semiconductor device

A STI process for a semiconductor device includes the steps of depositing a SiOxCy film where x<2 in a trench by using a biased high-density-plasma-enhanced CVD system, and heat treating the SiOxCy film in an oxidizing ambient to remove carbon and voids therein to form a stoichiometric SiO,film without causing volume expansion. The depositing step uses a higher ratio of deposited film/sputter-etched film for avoiding plasma damages to the silicon substrate.

Method for forming a shallow trench isolation structure

The present invention is directed to a process for manufacturing a semiconductor device. It includes a step for forming a fine wiring, and provides a process for uniformly and positively forming a film of a barrier metal, such as tantalum, for preventing the metal, such as copper, which becomes the first material for the wiring, from diffusing into a silicon oxide film. The process involves depositing an oxide of a barrier metal on a substrate which is formed with a via hole by a process such as CVD process. A high quality barrier metal film is formed by reducing the oxide by applying a negative potential to the oxide in a solution in which hydrogen ions are present. Subsequently an embedded wiring is formed by embedding the main metal by a plating process and the like and polishing to remove unnecessary portions.

Process for forming fine wiring

A multilevel interconnecting structure includes a plurality of interconnecting layers formed on a semiconductor substrate, a fluorine-doped oxide film for burying portions between the interconnecting layers, and an oxide film formed on the fluorine-doped oxide film, having a planarized surface, and not containing fluorine. A method of forming the multilevel interconnecting structure is also disclosed.

Multilevel interconnecting structure in semiconductor device and method of forming the same

A method for making a semiconductor device which has the steps of: (A) forming insulating film on a semiconductor substrate and then a plurality of lower wirings on the insulating film; (B) forming first insulating film with an overhang form to cover the surface of the lower wirings and the insulating film by using a plasma enhanced chemical vapor deposition method; (C) forming organic-included coating insulating film on the first insulating film by using a rotational coating method, (D) baking the organic-included coating insulating film; (E) etching back a part of the organic-included coating insulating film by using a dry-etching method; (F) forming second insulating film on the first insulating film and the organic-included coating insulating film by using the plasma enhanced chemical vapor deposition method; (G) polishing the second insulating film by using a chemical mechanical polishing method to planarize the surface, (H) etching a predetermined part of the first insulating film and the second insulating film to form a hole to reach the lower wirings; and (I) burying a metal material into the hole.

Method for making semiconductor device

A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.

Semiconductor device and fabrication process thereof

A multi-layer interconnection structure in a semiconductor device has a interlevel dielectric layer of three SiO.sub.2 films. The first SiO.sub.2 film has a small thickness not lower than 25 nm and is formed by a dual-frequency plasma enhanced CVD process using alkoxysilane as a reactive gas. The second SiO.sub.2 film has a large thickness ranging between 300 and 800 nm and is formed on the first SiO.sub.2 film by an atmospheric pressure CVD process using a mixture of alkoxysilane and ozone as a reactive gas. The third SiO.sub.2 film has a thickness of 50 nm and is flattened by an etch-back process of the same together with an overlying sacrificial spin-on glass film. A second layer interconnect pattern is formed on or above the flattened third SiO.sub.2 film with an excellent reliability.

Method of making a multi-layer interconnection structure

There is provided a method of fabricating a semiconductor device, including the steps of forming lower wiring layers on a semiconductor substrate, forming a first silicon oxide film by PECVD, forming a second silicon oxide film containing fluorine by PECVD so that the second silicon oxide film covers the first silicon oxide film and further so that portions thereof formed between the lower wiring layers have a top surface lower than a top surface of portions of the first silicon oxide film located on the lower wiring layers, forming a third silicon oxide film by PECVD so that the third silicon oxide film covers the second silicon oxide film and further so that portions of the third silicon film formed between the lower wiring layers have a top surface higher than a top surface of portions of the first silicon oxide film located on the lower wiring layers, the second silicon oxide film having a greater polishing rate than polishing rates of the first and third silicon oxide films, chemically and mechanically polishing the third and second silicon oxide films until a top surface of portions of the first silicon oxide film located on the lower wiring layers appears, and forming a fourth silicon oxide film by PECVD. The above mentioned method provides an interlayer insulating film having a low dielectric constant and a planarized surface suitable for multi-layer wiring.

Flat interlayer insulating film suitable for multi-layer wiring

Disclosed is a method of manufacturing a semiconductor device aimed at improving reliability of wiring, more particularly, of a via hole when a silicon oxide film formed by a high density plasma CVD process is used as an inter-level dielectric film in an integrated circuit having a multi-level wiring structure. When the multi-level wiring structure is formed on a semiconductor substrate, after underlying wiring is formed, a silicon oxide film is formed on the entire surface of the substrate by a high density plasma CVD process, and heat treated in inert gas or oxygen atmosphere at a temperature of 300.degree. C. or more but 500.degree. C. or less for 10 minutes or more. Excess hygrogen incorporated in the silicon oxide during the CVD process is removed by the above heat treatment. Subsequently, via holes are opened, and upper wiring is formed.

Method of manufacturing semiconductor devices having multi-level wiring

A method for fabricating a semiconductor device on a silicon substrate comprises the step of high-frequency plasma-treatment for through-hole before filling the through-hole with a metallic layer for connection. The plasma contains argon, oxygen and hydrogen atoms wherein the ratio of oxygen atoms to the total of the oxygen and hydrogen atoms in number is between 1/3 and 1/100. The silicon substrate is applied with a high-frequency bias voltage during the plasma treatment for acceleration of argon ion.

Method for manufacturing a multilevel interconnection structure

A semiconductor device comprising an insulating film at least partially containing a fluorine-containing film, formed above a semiconductor substrate, and a titanium nitride film formed on the insulating film. The above titanium film functions as a barrier metal film for barriering the diffusion of fluorine (F) atoms.

Growing community of inventors

Tokyo, Japan

Koji Kishimoto