Nec Corporation

Koji Kawata

Tadahiko Sugibayashi

Takahiro Hara

A DRAM according to the invention is provided with a memory cell array formed by arranging in the row and column directions one-transistor-one-capacitor type memory cells; bit lines, precharged at a prescribed timing, for performing the transfers of write-in/read-out data to and from the memory cells; a sense amplifier including a first transistor, whose drains are connected to the bit lines to bias the substrate to a prescribed potential, and a second transistor whose drains and sources are connected to the sources of the first transistor and a ground potential point, respectively, whose gates receive an activation control signal and whose substrate is biased to the same potential as the first transistor is, for amplifying the signals of said bit lines when activated; an intermediate potential generating circuit for supplying an intermediate potential which is substantially equal to 1/2 of the source potential to the opposite electrodes of said memories and to the bit lines; a power turn-on sensing circuit for generating a sensing signal which takes on an active level after the source potential reaches a prescribed level; and intermediate potential supply control means responsive to the sensing signal for controlling the supply of the intermediate potential to the bit lines. The current sources of said first and second transistors are cut off, power consumption is thereby saved and the occurrence of a latch-up phenomenon suppressed by suspending the supply of the intermediate potential to the bit lines during the period in which, immediately after the power is turned on, the substrate potential rises and the threshold values of the first and second transistors drop to keep these transistors in an ON state.

Semiconductor dynamic memory

A power supply circuit for a DRAM has a power-on detection circuit which detects when an external power supply potential reaches a predetermined potential and produces first and second detection signals, and an internal power supply circuit which generates an internal power supply potential. The power supply circuit further has a first intermediate potential generating circuit which generates a first intermediate potential from the external power supply potential and supplies it to an intermediate potential supplying node and, when the first detection signal is produced and the first intermediate potential reaches a predetermined potential, stops the supply of the first intermediate potential to the intermediate potential supplying node and the intermediate potential generating function, and a second intermediate potential generating circuit which generates a second intermediate potential from the internal power supply potential and, when the second detection signal is produced, supplies the second intermediate potential to the supplying node. The first intermediate potential generating circuit has a larger driving capability than that of the second intermediate potential generating circuit. It is made possible to shorten the rising time of the intermediate potential after the power is switched-on and to reduce the overall current consumption.

Growing community of inventors

Tokyo, Japan

Koji Kawata