Ricoh Company, Ltd.

Kioxia Corporation

Kabushiki Kaisha Toshiba

Olympus Optical Company, Ltd.

Toshiba Memory Corporation

Hitachi Koki Co., Ltd.

Oki Data Corporation

Astellas Pharma Gmbh

Olympus Corporation

Sumco Corporation

Canon Kabushiki Kaisha

Nec Corporation

Oki Electric Industry Co., Ltd.

Ricoh Printing Systems, Ltd.

Sumitomo Mitsubishi Silicon Corporation

Koji Kato

Tomohiro Kubota

Yoshiyuki Shimizu

Kenzo Tatsumi

Tomofumi Yoshida

Hirobumi Ooyoshi

Yoshihiro Kawakami

Yoshihiko Kamata

Tsukasa Kobayashi

Yuki Shimizu

Mai Shimizu

Mario Sako

Takeshi Hioka

Hiroshi Maejima

Tatsuya Suzuki

Masayasu Anzai

Shigeo Ohshima

Yuui Shimizu

Yoshitaka Fujinuma

Yoshinao Suzuki

Akira Inoue

Satoshi Miyazaki

Hitoshi Shiga

Takashi Suzuki

Hiroyuki Mabuchi

Toshifumi Hashimoto

Hiroyuki Moritomo

Yasuo Takuma

Yukihiko Sugita

Tsuneaki Kawanishi

Masanori Miura

Takashi Okamura

Masayuki Ainoya

Shigeru Umeno

Masahiro Kamoshida

Yoichi Hayakawa

Kunio Yokoyama

Hiroyuki Ando

Masayoshi Ishii

Ippei Sato

Tsutomu Nakagawa

Shunichiro Hachiya

Daisuke Kaga

Mitsuhiro Noguchi

Takuya Futatsuyama

Sumio Kawai

Kikuko Sugimae

Shinya Takahashi

Keiji Kunishige

Hiroyuki Kutsukake

Keita Takahashi

Eietsu Takahashi

Teruaki Mitsuya

Hiroshi Nagata

Hideaki Yoshida

Yasuo Asakura

Keiichi Mori

Kenji Nozawa

Shigeru Kato

Hiroshi Terada

Junji Shirakawa

Takeshi Nakano

Moriya Katagiri

Toshiyuki Noguchi

Noriyuki Kawano

Naoki Fujii

Masayuki Watanabe

Masato Endo

Yutaka Naitoh

Takao Yamazaki

Takayuki Kijima

Noriyasu Kumazaki

Yasushi Hashimoto

Tomonori Kurosawa

Hisao Okada

Kenji Gomikawa

Hideki Kubota

Tatsuji Higuchi

Minoru Hara

Junzo Sakurai

Kazuhiro Yokoyama

Tokuhito Sasaki

Takashi Inoue

Hiroyuki Ohtake

Kazuhide Yoneya

Naoyuki Masuda

Tadashi Terasaka

Isamu Komatsu

Minoru Seino

Hidenori Azami

Shunji Matsutani

Issei Tsukamoto

Sunao Imada

Akira Terakado

Kazunori Kamijo

Yuta Fukuda

Yuichiro Suzuki

Tatsuho Yoshida

Shigeru Iwase

Toru Kontani

A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

Semiconductor memory device

A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Semiconductor storage device

A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.

According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.

A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

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Tokyo, Japan

Koji Kato