Toshiba Ceramics Co., Ltd.

Covalent Materials Corporation

Globalwafers Japan Co., Ltd.

Shibaura Mechatronics Corporation

Tohoku University

Koji Izunome

Takeshi Senda

Kazuhiko Kashima

Hiromichi Isogai

Susumu Maeda

Haruo Sudo

Tatsuhiko Aoki

Eiji Toyoda

Koji Araki

Kumiko Murayama

Yoshinori Hayashi

Tetsuo Endoh

Takashi Ishikawa

Hisatsugu Kurita

Etsuo Fukuda

Miyuki Shimizu

Kazuhiko Hamatani

Hiroyuki Naraidate

Masato Igarashi

Shoji Ikeda

Reiko Yoshimura

Tsukasa Tada

Akihiko Kobayashi

Hiroyuki Saito

Moriya Miyashita

Takao Sakamoto

Senlin Fu

Hideaki Takano

Kazutaka Kamijo

Yoichiro Mochizuki

Makoto Kyoya

Hiromi Nagahama

Hiroaki Yuda

Atsushi Tanabe

Hisashi Matsumura

A silicon wafer is a Czochralski wafer formed of silicon. The wafer includes a bulk layer having an oxygen concentration of 0.5×10/cmor more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×10/cmor more.

Silicon wafer and method for producing silicon wafer

A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×10atoms/cmor more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Method for producing three-dimensional structure, method for producing vertical transistor, vertical transistor wafer, and vertical transistor substrate

A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface regionwhich is a defect-free region and a bulk regionincluding void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

Silicon wafer and method for heat-treating silicon wafer

A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T) of 1300&#xb0; C. or more, but less than 1380&#xb0; C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7&#xd7;10atoms/cmor more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.

Method of manufacturing single crystal silicon wafer from ingot grown by Czocharlski process with rapid heating/cooling process

The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to Tof 1300&#xb0; C. or higher and the melting point of silicon or lower, keeping the wafer at T, rapidly cooling the wafer to Tof 400-800&#xb0; C. and keeping the wafer at T; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T, rapidly heating the wafer from Tto Tof 1250&#xb0; C. or higher and the melting point of silicon or lower, keeping the wafer at Tand rapidly cooling the wafer.

Method for heat treating a silicon wafer

In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200&#xb0; C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.

Method of heat treating silicon wafer

In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300&#xb0; C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.

Manufacturing method for silicon wafer

An image pickup device disposed in a predetermined position relative to a surface of a strained silicon wafer photographs the surface of the strained silicon wafer in a plurality of rotation angle positions on photographing conditions under which bright lines appearing on the surface of the strained silicon wafer can be photographed, in an environment where a light source device illuminates the surface of the strained silicon wafer which is rotating. A composite image in a predetermined angle position is generated from surface images of the strained silicon wafer in a plurality of rotation angle positions obtained by the image pickup device.

Surface inspection apparatus and surface inspection method for strained silicon wafer

A surface inspection apparatus, for inspecting a plurality of surfaces formed in a peripheral edge portion of a plate-like object, includes a image pickup mechanism, which photographs the peripheral edge portion of the plate-like object having a plurality of surfaces, and an image processing device, which processes an image obtained by the photographing device. The image pickup mechanism includes an optical system which guides images of the plurality of surfaces of the plate-like object in one direction, and a camera unit having an image pickup surface, on which the images of the plurality of surfaces guided by the optical system in the one direction are formed.

Surface inspection apparatus and surface inspection method

A manufacturing method for producing a stained silicon wafer has the steps of forming an SiGecomposition-graded layer of which Ge concentration is stepwisely increased on a single crystal silicon substrate, forming an SiGeuniform composition layer of which Ge concentration is constant on the SiGecomposition-graded layer, forming a stain-relaxed SiGelayer of which Ge concentration y is constant while y satisfies relationship of 0.5x&#x2266;y&#x3c;x on the SiGeuniform composition layer and epitaxially growing a strained Si layer on the strain-relaxed SiGelayer.

Manufacturing method for strained silicon wafer

A method for manufacturing a strained silicon wafer, having steps of a first step of preparing a single crystal silicon substrate, a second step of forming a graded SiGe layer on the substrate, the graded SiGe layer having a first Ge composition ratio increased stepwisely from 5 to 60% at atomic ratio, a third step of forming a SiGe constant composition layer on the graded SiGe layer, the SiGe constant composition layer having a Ge composition ratio substantially equal to the Ge composition ratio on a surface of the-graded SiGe layer and a fourth step of forming a strained Si layer on the SiGe constant composition layer. The second through fourth steps are performed under the reduced pressure atmosphere while the single crystal silicon substrate is rotated in a circumferential direction at a rate from 300 rpm to 1500 rpm.

A semiconductor substrate includes a support substratehas gettering sitesfor gettering impurity metal, an embedded insulating filmwhich is provided on the support substrateand contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer)provided on the embedded insulating film

Semiconductor substrate comprising a support substrate which comprises a gettering site

A wafer inspection apparatus has a supporting means () for rotatably supporting a wafer (W) formed of a disk, a circumferential edge imaging means () for imaging a circumferential edge (S) of the wafer (W) that is supported by the supporting means for rotation, a notch imaging means () for imaging a notch (N), a notch illumination part () for illuminating the notch (N), and a control means () for processing image data imaged by the circumferential edge imaging means () and the notch imaging means (). The circumferential edge imaging means () has a plurality of imaging cameras () for imaging a plurality of different parts in a thickness direction of the circumferential edge of the wafer (W). The different parts of the circumferential edge (S) of the wafer (W) include an apex at right angles to a surface of the wafer (W) and a front side bevel and a back side bevel inclined relative to the apex. The notch imaging means () for the wafer (W) having the notch (N) has a plurality of imaging cameras () for imaging different parts in the thickness direction of the notch (N).

Wafer inspection apparatus

A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 &#x3bc;m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.

Growing community of inventors

Niigata, Japan

Koji Izunome