Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Fujitsu Semiconductor Limited

Koji Hosono

Kenichi Imamiya

Hiroshi Nakamura

Koichi Kawai

Hiroshi Maejima

Toshio Yamamura

Ken Takeuchi

Takuya Futatsuyama

Dai Nakamura

Tomoharu Tanaka

Mitsuhiro Noguchi

Masaru Koyanagi

Hiroyuki Kutsukake

Kazushige Kanda

Toshiaki Edahiro

Kenji Gomikawa

Takeshi Shimane

Takashi Aoi

Noboru Shibata

Tamio Ikehashi

Naoya Tokiwa

Toshihiko Himeno

Shigeo Ohshima

Masahiro Yoshihara

Tadashi Yasufuku

Masanobu Shirakawa

Satoru Takase

Koichi Fukuda

Takeshi Nakano

Tomonori Kurosawa

Masatsugu Kojima

Toshifumi Shano

Mikito Nakabayashi

Yuri Terada

Takashi Mori

Yasuo Itoh

Hidehiro Shiga

Takahiko Sasaki

Yasuyuki Fukuda

Tomoki Nakagawa

Katsuaki Sakurai

Youichi Kai

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Non-volatile semiconductor storage device

A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

Non-volatile semiconductor memory device including application of different voltages to memory cells based on their proximity to a selected memory cell

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Semiconductor integrated circuit adapted to output pass/fail results of internal operations

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

Semiconductor memory device

A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.

Method for controlling a non-volatile semiconductor memory device

A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.

Nonvolatile semiconductor memory device and control method thereof

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Koji Hosono